devpriv->ao[chan] = data[0];
if(boardtype.reg_type == ni_reg_m_series)
+ {
ni_writew(data[0] ^ invert, M_Offset_DAC_Direct_Data(chan));
+ }
else
ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
devpriv->ao_cmd2=0;
devpriv->ao_mode1=0;
devpriv->ao_mode2=0;
- devpriv->ao_mode3=0;
+ if(boardtype.reg_type == ni_reg_m_series)
+ devpriv->ao_mode3 = AO_Last_Gate_Disable;
+ else
+ devpriv->ao_mode3 = 0;
+ devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
devpriv->ao_trigger_select=0;
if(boardtype.reg_type & ni_reg_6xxx_mask){
ao_win_out(0x3, AO_Immediate_671x);
ao_win_out(CLEAR_WG, AO_Misc_611x);
}
+ devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
return 0;
}
ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
}
+ ni_writeb(0x0, M_Offset_AO_Calibration);
}
printk("\n");
AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
AO_FIFO_Enable = 1 << 10,
AO_TMRDACWR_Pulse_Width = 1 << 12,
+ AO_Number_Of_DAC_Packages = 1 << 14, // 1 for "single" mode, 0 for "dual"
};
#define Write_Strobe_0_Register 82
#define Write_Strobe_1_Register 83