some assorted MITE bugs.
prealloc_bufsz=async->prealloc_bufsz;
continuous_aq = (async->cmd.stop_src == TRIG_NONE? 1:0);
- //if(continuous_aq) {
- // len = prealloc_bufsz;
- //}
+ if(continuous_aq) {
+ len = prealloc_bufsz;
+ }
- //len = min(cmd->scan_end_arg*cmd->stop_arg*sizeof(sampl_t), async->data_len);
if(async->data_len<len) {
printk("<1>Comedi Error: preallocated DMA buffer is too small to hold the samples.");
}
To make a looping ring for continuous acquisition,
mite->ring[i-1].next = virt_to_bus(mite->ring);
*/
- mite->ring[i].count=0;
+ //mite->ring[i].count=0;
- //if (continuous_aq&&(i>0)) {
- // mite->ring[i-1].next = virt_to_bus(mite->ring+0);
- //}else {
- // mite->ring[i].count=0;
- //}
+ if (continuous_aq&&(i>0)) {
+ mite->ring[i-1].next = virt_to_bus(mite->ring+0);
+ }else {
+ mite->ring[i].count=0;
+ }
MDPRINTK("i was %d, size_so_far was %d\n",i,size_so_far);
rt_printk("ni_mio_common: ai error a_status=%04x\n",
status);
ni_mio_print_status_a(status);
+
+ //TIM 5/11/01
+ win_out(AI_Error_Interrupt_Ack, Interrupt_A_Ack_Register);
+
+ #ifndef PCIDMA
ni_handle_fifo_dregs(dev);
+ #endif \r
+
//TIM 4/17/01
//win_out(0x0000,Interrupt_A_Enable_Register);
//turn off all AI interrupts
AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
AI_FIFO_Interrupt_Enable,0);
+
ni_ai_reset(dev,dev->subdevices);//added by tim
comedi_done(dev,s);
return;
#else
win_out((0<<6)|0x0000,AI_Mode_3_Register); /* generate FIFO interrupts on non-empty */
#endif
+ /* TIM 5/11/01
+ 0xA4A0 causes overrun errors at high speeds. 0xA420 fixes it,
+ but I haven't tested to see if it breaks something else. I don't think it would*/
+ #ifdef PCIDMA
+ win_out(0xA420,AI_Personal_Register);
+ #else
win_out(0xa4a0,AI_Personal_Register); /* ? */
+ #endif
win_out(0x032e,AI_Output_Control_Register);
win_out(0x0060,AI_Trigger_Select_Register); /* trigger source */
#define AI_FIFO_Request_St 0x0002
#define Pass_Thru_0_Interrupt_St 0x0001
+#define AI_Status_2_Register 5
+
#define Interrupt_B_Ack_Register 3
#define AO_Status_1_Register 3
#define Interrupt_B_St _bit15