for(i=0;i<COMEDI_NDEVICES;i++){
char name[20];
+ struct class_device *class_dev;
sprintf(name, "comedi%d", i);
devfs_register(NULL, name, DEVFS_FL_DEFAULT,
COMEDI_MAJOR, i, 0666 | S_IFCHR, &comedi_fops, NULL);
- struct class_device *class_dev = COMEDI_CLASS_DEVICE_CREATE(comedi_class, 0,
+ class_dev = COMEDI_CLASS_DEVICE_CREATE(comedi_class, 0,
MKDEV(COMEDI_MAJOR, i), NULL, "comedi%i", i);
comedi_devices[i].devt = class_dev->devt;
comedi_devices[i].minor = MINOR(class_dev->devt);
static int ni_65xx_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
comedi_insn *insn,lsampl_t *data)
{
- if(insn->n != 2) return -EINVAL;
- const unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
+ unsigned base_bitfield_channel;
const unsigned max_ports_per_bitfield = 5;
unsigned read_bits = 0;
unsigned j;
+ if(insn->n != 2) return -EINVAL;
+ base_bitfield_channel = CR_CHAN(insn->chanspec);
for(j = 0; j < max_ports_per_bitfield; ++j)
{
const unsigned port = sprivate(s)->base_port + ni_65xx_port_by_channel(base_bitfield_channel) + j;
+ unsigned base_port_channel;
+ unsigned port_mask, port_data, port_read_bits;
+ int bitshift;
if(port >= ni_65xx_total_num_ports(board(dev))) break;
- const unsigned base_port_channel = port * ni_65xx_channels_per_port;
- unsigned port_mask = data[0];
- unsigned port_data = data[1];
- int bitshift = base_port_channel - base_bitfield_channel;
+ base_port_channel = port * ni_65xx_channels_per_port;
+ port_mask = data[0];
+ port_data = data[1];
+ bitshift = base_port_channel - base_bitfield_channel;
if(bitshift >= 32 || bitshift <= -32) break;
if(bitshift > 0)
{
port_data &= 0xff;
if(port_mask)
{
+ unsigned bits;
private(dev)->output_bits[port] &= ~port_mask;
private(dev)->output_bits[port] |= port_data & port_mask;
- unsigned bits = private(dev)->output_bits[port];
+ bits = private(dev)->output_bits[port];
if(board(dev)->invert_outputs) bits = ~bits;
writeb(bits, private(dev)->mite->daq_io_addr + Port_Data(port));
// rt_printk("wrote 0x%x to port %i\n", bits, port);
}
- unsigned port_read_bits = readb(private(dev)->mite->daq_io_addr + Port_Data(port));
+ port_read_bits = readb(private(dev)->mite->daq_io_addr + Port_Data(port));
// rt_printk("read 0x%x from port %i\n", port_read_bits, port);
if(bitshift > 0)
{
static int ni_65xx_attach(comedi_device *dev,comedi_devconfig *it)
{
comedi_subdevice *s;
+ unsigned i;
int ret;
printk("comedi%d: ni_65xx:",dev->minor);
s->private = ni_65xx_alloc_subdevice_private();
if(s->private == NULL) return -ENOMEM;
sprivate(s)->base_port = 0;
- unsigned i;
for(i = 0; i < board(dev)->num_dio_ports; ++i)
{
// configure all ports for input
s->insn_bits = ni_65xx_intr_insn_bits;
s->insn_config = ni_65xx_intr_insn_config;
- unsigned i;
for(i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i)
{
writeb(0x00, private(dev)->mite->daq_io_addr + Filter_Enable(i));
// offset = 1 << (boardtype.adbits - 1);
if((list[0] & CR_ALT_SOURCE))
{
+ unsigned bypass_bits;
chan = CR_CHAN(list[0]);
range = CR_RANGE(list[0]);
range_code = ni_gainlkup[boardtype.gainlkup][range];
dither = ((list[0] & CR_ALT_FILTER) != 0);
- unsigned bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
+ bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
bypass_bits |= chan;
bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
}
for(i=0;i<n_chans;i++)
{
+ comedi_krange *krange;
chan = CR_CHAN(chanspec[i]);
range = CR_RANGE(chanspec[i]);
- comedi_krange *krange = s->range_table->range + range;
+ krange = s->range_table->range + range;
invert = 0;
conf = 0;
switch(krange->max - krange->min)
AO_UPDATE_Output_Select(1),
AO_Output_Control_Register);
}else{
+ unsigned bits;
devpriv->ao_mode1&=~AO_Multiple_Channels;
- unsigned bits = AO_UPDATE_Output_Select(1);
+ bits = AO_UPDATE_Output_Select(1);
if(boardtype.reg_type == ni_reg_m_series)
bits |= AO_Number_Of_Channels(0);
else
s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
if(boardtype.reg_type == ni_reg_m_series)
{
+ unsigned i;
s->n_chan = 16;
ni_writew(s->state, M_Offset_PFI_DO);
- unsigned i;
for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
{
ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
{
+ unsigned pfi_reg_index;
+ unsigned array_offset;
if((source & 0x1f) != source) return -EINVAL;
- const unsigned pfi_reg_index = 1 + chan / 3;
- const unsigned array_offset = pfi_reg_index - 1;
+ pfi_reg_index = 1 + chan / 3;
+ array_offset = pfi_reg_index - 1;
devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
/* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
* 20 MHz for most timing clocks */
static const unsigned target_picosec = 12500;
+ static const unsigned fudge_factor_80_to_20Mhz = 4;
int best_period_picosec = 0;
for(div = 1; div <= max_div; ++div)
{
}
*freq_divider = best_div;
*freq_multiplier = best_mult;
- static const unsigned fudge_factor_80_to_20Mhz = 4;
*actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
return 0;
}
static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
{
- if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
- // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
static const unsigned min_period_ns = 50;
static const unsigned max_period_ns = 1000;
+ static const unsigned timeout = 1000;
+ unsigned pll_control_bits;
+ unsigned freq_divider;
+ unsigned freq_multiplier;
+ unsigned i;
+ int retval;
+ if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
+ // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
if(period_ns < min_period_ns || period_ns > max_period_ns)
{
rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
}
devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
- unsigned pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
+ pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit;
devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
- int retval;
- unsigned freq_divider;
- unsigned freq_multiplier;
switch(source)
{
case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
// rt_printk("clock_ns=%d\n", devpriv->clock_ns);
ni_writew(pll_control_bits, M_Offset_PLL_Control);
devpriv->clock_source = source;
- unsigned i;
- static const unsigned timeout = 1000;
/* it seems to typically take a few hundred microseconds for PLL to lock */
for(i = 0; i < timeout; ++i)
{