Makefile: Quote all $@ and $< expansion

To protect against spaces and special characters in their values.

diff --git a/Makefile b/Makefile
index 44af03efa61438e9641eecdb7d1ea61f368c0e55..97390cb190a53e04a9b7435f45b7dff86fa9ad2f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -120,11 +120,11 @@ dist:
 # certainly allowed to go that route if you wish.
 .SECONDEXPANSION:
 $(C_PROGRAMS): % : $$($$(@)_OBJECTS)
-       $(CC) $(LDFLAGS) -o $@ $^ $($(@)_LIBS)
+       $(CC) $(LDFLAGS) -o "$@" $^ $($(@)_LIBS)
 
 .SECONDEXPANSION:
 $(CXX_PROGRAMS): % : $$($$(*)_OBJECTS)
-       $(CXX) $(LDFLAGS) -o $@ $^ $($(@)_LIBS)
+       $(CXX) $(LDFLAGS) -o "$@" $^ $($(@)_LIBS)
 
 # target: run - use the program for its intended purpose
 # Here we just execute RUN_PROGRAM, but you could also use something
@@ -152,12 +152,12 @@ run: $(PROGRAMS)
 # for example, try
 #    $ make CXX=/usr/local/bin/g++ CXXFLAGS=-Wall
 %.o: %.cpp
-       $(CXX) $(CXXFLAGS) -c $<
+       $(CXX) $(CXXFLAGS) -c "$<"
 
 # Pattern rule for compiling object files from C source
 # The comments from the C++ rule above also apply here
 %.o: %.c
-       $(CC) $(CFLAGS) -c $<
+       $(CC) $(CFLAGS) -c "$<"
 
 # target: print-% - display a variable value (e.g. print-PROGRAMS)
 # Take some of the mystery out of variable manipulation.  For example,