Added a little more on how the ni windows drivers enables mite burst

mode.

diff --git a/comedi/drivers/mite.c b/comedi/drivers/mite.c
index 267dd4d5f9bfd11bb0bf27603c6d228cbdb612ac..a56041183ffae19de7227f2920f7f4f1cb7fb768 100644 (file)
--- a/comedi/drivers/mite.c
+++ b/comedi/drivers/mite.c
@@ -167,15 +167,11 @@ int mite_setup(struct mite_struct *mite)
        /* make sure dma bursts work.  I got this from running a bus analyzer
        on a pxi-6281 and a pxi-6713.  6713 powered up with register value
        of 0x61f and bursts worked.  6281 powered up with register value of
-       0x1f and bursts didn't work.  The NI windows driver read the register, then
-       wrote 0x61f to it, so it looked like it was trying to preserve some
-       of the register bits instead of overwriting them all, I am only
-       guessing which ones though.  Later I'll try initializing the register with
-       all ones and all zeros to see if I can determine which bits the
-       windows driver is really changing.
+       0x1f and bursts didn't work.  The NI windows driver reads the register,
+       then does a bitwise-or of 0x600 with it and writes it back.
        */
        unknown_dma_burst_bits = readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
-       unknown_dma_burst_bits |= 0x600;
+       unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
        writel(unknown_dma_burst_bits, mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 
        csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);

diff --git a/comedi/drivers/mite.h b/comedi/drivers/mite.h
index b7ac55ef38d5dfcf8f16d0c8dde9281d875a24e3..0569f02821b745ce51cd5bf1b55bbf4b62597a2c 100644 (file)
--- a/comedi/drivers/mite.h
+++ b/comedi/drivers/mite.h
@@ -153,6 +153,9 @@ static inline int CHAN_OFFSET(int channel)
 
 enum mite_registers
 {
+       /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
+       written and read back.  The bits 0x1f always read as 1.
+       The rest always read as zero. */
        MITE_UNKNOWN_DMA_BURST_REG = 0x28,
        MITE_IODWBSR = 0xc0, //IO Device Window Base Size Register
        MITE_IODWBSR_1 = 0xc4, // IO Device Window Base Size Register 1
@@ -240,6 +243,11 @@ static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned order)
        return (order - 1) & 0x1f;
 }
 
+enum MITE_UNKNOWN_DMA_BURST_bits
+{
+       UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
+};
+
 static inline int mite_csigr_version(u32 csigr_bits)
 {
        return csigr_bits & 0xf;