case INSN_CONFIG_DIO_INPUT:
case INSN_CONFIG_ARM:
case INSN_CONFIG_DISARM:
+ case INSN_CONFIG_RESET_COUNT:
if(insn->n == 1) return 0;
break;
case INSN_CONFIG_DIO_QUERY:
return 0;
}
-void ni_tio_init_counter(struct ni_gpct *counter)
+static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
{
- /* reset counter */
counter->write_register(counter, Gi_Reset_Bit(counter->counter_index),
NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
+}
+
+void ni_tio_init_counter(struct ni_gpct *counter)
+{
+ ni_tio_reset_count_and_disarm(counter);
/* initialize counter registers */
counter->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] = 0x0;
counter->write_register(counter, counter->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
case INSN_CONFIG_GET_GATE_SRC:
return ni_tio_get_gate_src(counter, data[1], &data[2]);
break;
+ case INSN_CONFIG_RESET_COUNT:
+ ni_tio_reset_count_and_disarm(counter);
+ return 0;
+ break;
default:
break;
}
INSN_CONFIG_ARM = 31,
INSN_CONFIG_DISARM = 32,
INSN_CONFIG_GET_COUNTER_STATUS = 33,
+ INSN_CONFIG_RESET_COUNT = 34,
INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, // Use CTR as single pulsegenerator
INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, // Use CTR as pulsetraingenerator
INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, // Use the counter as encoder