devpriv->ps_BoardInfo = this_board;
devpriv->i_IobaseReserved=io_addr[3];
printk ("\nioremap begin");
- devpriv->dw_AiBase=(UINT) ioremap(io_addr[3],this_board->i_IorangeBase3);
+ devpriv->dw_AiBase=(ULONG_PTR) ioremap(io_addr[3],this_board->i_IorangeBase3);
printk ("\nioremap end");
}
#define VOID void
#define UINT unsigned int
-#define ULONG unsigned long
+#define ULONG unsigned int /* 32-bit */
#define USHORT unsigned short
#define PUSHORT unsigned short *
#define INT int
#define HIWORD(W) (USHORT )(((W)>>16)&0xFFFF)
#define MAKEDWORD(H,L) (UINT )((L)|( (H)<<16) )
-#define DWORD unsigned long
+#define ULONG_PTR unsigned long
+#define DWORD unsigned int /* 32-bit */
#define WORD unsigned short
#define ADDI_ENABLE 1
INT i_IobaseAmcc; // base+size for AMCC chip
INT i_IobaseAddon; //addon base address
INT i_IobaseReserved;
- DWORD dw_AiBase;
+ ULONG_PTR dw_AiBase;
struct pcilst_struct *amcc; // ptr too AMCC data
UINT master; // master capable
BYTE allocated; // we have blocked card
/* The selected TTL output port is wrong */
/*****************************************/
- printk("\nPort selection error %lX", devpriv->ul_TTLPortConfiguration[0]);
+ printk("\nPort selection error %lX", (unsigned long)devpriv->ul_TTLPortConfiguration[0]);
i_ReturnValue = -102;
}
}
if (sizeof(jr3_channel_t) != 0xc00) {
printk("sizeof(jr3_channel_t) = %x [expected %x]\n",
- sizeof(jr3_channel_t), 0xc00);
+ (unsigned)sizeof(jr3_channel_t), 0xc00);
return -EINVAL;
}
p = dev->subdevices[i].private;
p->channel = &devpriv->iobase->channel[i].data;
- printk("p->channel %p %p (%x)\n",
+ printk("p->channel %p %p (%tx)\n",
p->channel, devpriv->iobase,
- (int)(p->channel) - (int)(devpriv->iobase));
+ ((char *)(p->channel) - (char *)(devpriv->iobase)));
p->channel_no = i;
for (j = 0 ; j < 8 ; j++) {
int k;
}
};
-#define ADDR_REG(reg) (int)((int)((s526_board *)dev->iobase) + reg)
-#define ADDR_CHAN_REG(reg, chan) (int)((int)((s526_board *)dev->iobase) + reg + chan * 8)
+#define ADDR_REG(reg) (dev->iobase + (reg))
+#define ADDR_CHAN_REG(reg, chan) (dev->iobase + (reg) + (chan) * 8)
/*
* Useful for shorthand access to the particular board structure
}
dev->iobase=iobase;
- printk("iobase=0x%lux\n", dev->iobase);
+ printk("iobase=0x%lx\n", dev->iobase);
/*** make it a little quieter, exw, 8/29/06
for (i = 0; i < S526_NUM_PORTS; i++) {
cmReg.reg.reserved = 0;
n = 0;
- printk("Mode reg=0x%04x, 0x%04x\n", cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
+ printk("Mode reg=0x%04x, 0x%04lx\n", cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
udelay(1000);
printk("Read back mode reg=0x%04x\n", inw(ADDR_CHAN_REG(REG_C0M, n)));
printk("Current registres:\n");
for (i = 0; i < S526_NUM_PORTS; i++) {
- printk("0x%02x: 0x%04x\n", ADDR_REG(s526_ports[i]), inw(ADDR_REG(s526_ports[i])));
+ printk("0x%02lx: 0x%04x\n", ADDR_REG(s526_ports[i]), inw(ADDR_REG(s526_ports[i])));
}
return 1;
}
return -ENOMEM;
}
- devpriv->ANABuf.PhysicalBase=(void*)appdma;
+ devpriv->ANABuf.PhysicalBase=appdma;
- DEBUG("s626_attach: AllocDMAB ADC Logical=0x%x, bsize=%d, Physical=0x%x\n",
- (uint32_t) devpriv->ANABuf.LogicalBase, DMABUF_SIZE, (uint32_t)devpriv->ANABuf.PhysicalBase);
+ DEBUG("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n",
+ devpriv->ANABuf.LogicalBase, DMABUF_SIZE, (uint32_t)devpriv->ANABuf.PhysicalBase);
devpriv->allocatedBuf++;
return -ENOMEM;
}
- devpriv->RPSBuf.PhysicalBase=(void*)appdma;
+ devpriv->RPSBuf.PhysicalBase=appdma;
- DEBUG("s626_attach: AllocDMAB RPS Logical=0x%x, bsize=%d, Physical=0x%x\n",
- (uint32_t) devpriv->RPSBuf.LogicalBase, DMABUF_SIZE, (uint32_t)devpriv->RPSBuf.PhysicalBase);
+ DEBUG("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n",
+ devpriv->RPSBuf.LogicalBase, DMABUF_SIZE, (uint32_t)devpriv->RPSBuf.PhysicalBase);
devpriv->allocatedBuf++;
devpriv->ai_cmd_running=0;
if (devpriv->base_addr && (devpriv->allocatedBuf==2)){
- uint32_t *pPhysBuf;
+ dma_addr_t pPhysBuf;
uint16_t chan;
// enab DEBI and audio pins, enable I2C interface.
// single DWORD will be transferred each time a DMA transfer is
// enabled.
- pPhysBuf = (uint32_t *)devpriv->ANABuf.PhysicalBase + DAC_WDMABUF_OS;
+ pPhysBuf = devpriv->ANABuf.PhysicalBase + (DAC_WDMABUF_OS * sizeof(uint32_t));
WR7146( P_BASEA2_OUT, (uint32_t) pPhysBuf ); // Buffer base adrs.
- WR7146( P_PROTA2_OUT, (uint32_t) (pPhysBuf + 1) ); // Protection address.
+ WR7146( P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t)) ); // Protection address.
// Cache Audio2's output DMA buffer logical address. This is
// where DAC data is buffered for A2 output DMA transfers.
// here; this allows us to produce a longer delay than is
// possible with NOPs because each RPS_JUMP flushes the RPS'
// instruction prefetch pipeline.
- JmpAdrs = (uint32_t)devpriv->RPSBuf.PhysicalBase + (uint32_t)pRPS - (uint32_t)devpriv->RPSBuf.LogicalBase;
+ JmpAdrs = (uint32_t)devpriv->RPSBuf.PhysicalBase + (uint32_t)((unsigned long)pRPS - (unsigned long)devpriv->RPSBuf.LogicalBase);
for ( i = 0; i < ( 10 * RPSCLK_PER_US / 2); i++ ) {
JmpAdrs += 8; // Repeat to implement time delay:
* pRPS++= RPS_JUMP ; // Jump to next RPS instruction.
static void CloseDMAB (comedi_device *dev,DMABUF * pdma,size_t bsize )
{
- void *vbptr, *vpptr;
+ void *vbptr;
+ dma_addr_t vpptr;
DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n");
if (pdma == NULL)
vpptr=pdma->PhysicalBase;
if (vbptr)
{
- pci_free_consistent (devpriv->pdev, bsize, vbptr,
- (int) vpptr);
+ pci_free_consistent (devpriv->pdev, bsize, vbptr, vpptr);
pdma->LogicalBase = 0;
pdma->PhysicalBase = 0;
- DEBUG ("CloseDMAB(): Logical=0x%x, bsize=%d, Physical=0x%x\n", (uint32_t) vbptr, bsize, (uint32_t) vpptr);
+ DEBUG ("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n", vbptr, bsize, (uint32_t) vpptr);
}
}
typedef struct bufferDMA
{
- void *PhysicalBase;
+ dma_addr_t PhysicalBase;
void *LogicalBase;
uint32_t DMAHandle;
} DMABUF;
oldfs = get_fs();
set_fs(KERNEL_DS);
- f->f_op->ioctl(f->f_dentry->d_inode, f, FIONREAD, (int)&result);
+ f->f_op->ioctl(f->f_dentry->d_inode, f, FIONREAD, (unsigned long)&result);
set_fs(oldfs);
return result;
}
// Set speed
struct termios settings;
- f->f_op->ioctl(f->f_dentry->d_inode, f, TCGETS, (int)&settings);
+ f->f_op->ioctl(f->f_dentry->d_inode, f, TCGETS, (unsigned long)&settings);
// printk("Speed: %d\n", settings.c_cflag & (CBAUD | CBAUDEX));
settings.c_iflag = 0;
settings.c_oflag = 0;
case 115200: { settings.c_cflag |= B115200; } break;
default: { settings.c_cflag |= B9600; } break;
}
- f->f_op->ioctl(f->f_dentry->d_inode, f, TCSETS, (int)&settings);
+ f->f_op->ioctl(f->f_dentry->d_inode, f, TCSETS, (unsigned long)&settings);
// printk("Speed: %d\n", settings.c_cflag & (CBAUD | CBAUDEX));
}
{
// Set low latency
struct serial_struct settings;
- f->f_op->ioctl(f->f_dentry->d_inode, f, TIOCGSERIAL, (int)&settings);
+ f->f_op->ioctl(f->f_dentry->d_inode, f, TIOCGSERIAL, (unsigned long)&settings);
settings.flags |= ASYNC_LOW_LATENCY;
- f->f_op->ioctl(f->f_dentry->d_inode, f, TIOCSSERIAL, (int)&settings);
+ f->f_op->ioctl(f->f_dentry->d_inode, f, TIOCSSERIAL, (unsigned long)&settings);
}
set_fs(oldfs);
sprintf(port, "/dev/ttyS%d", devpriv->port);
devpriv->tty = filp_open(port, 0, O_RDWR);
if (IS_ERR(devpriv->tty)) {
- printk("serial_2002: file open error = %x\n", (int)devpriv->tty);
+ printk("serial_2002: file open error = %ld\n", PTR_ERR(devpriv->tty));
} else {
typedef struct {
int kind;