comedi/drivers/ni_tio.c

   1 /*
   2   comedi/drivers/ni_tio.c
   3   Support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16
  17   You should have received a copy of the GNU General Public License
  18   along with this program; if not, write to the Free Software
  19   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23 Driver: ni_tio.o
  24 Description: National Instruments general purpose counters
  25 Devices:
  26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  27         Herman.Bruyninckx@mech.kuleuven.ac.be,
  28         Wim.Meeussen@mech.kuleuven.ac.be,
  29         Klaas.Gadeyne@mech.kuleuven.ac.be,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Updated: Thu Nov 16 09:50:32 EST 2006
  32 Status: experimental
  33
  34 This module is not used directly by end-users.  Rather, it
  35 is used by other drivers (for example ni_660x and ni_pcimio)
  36 to provide support for NI's general purpose counters.  It was
  37 originally based on the counter code from ni_660x.c and
  38 ni_mio_common.c.
  39
  40 References:
  41 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  42 DAQ 6601/6602 User Manual (NI 322137B-01)
  43 340934b.pdf  DAQ-STC reference manual
  44
  45 */
  46
  47 #include "ni_tio.h"
  48 #include "mite.h"
  49
  50 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter, unsigned generic_clock_source);
  51 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
  52
  53 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
  54 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
  55 MODULE_LICENSE("GPL");
  56
  57 static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned counter_index)
  58 {
  59         switch(counter_index)
  60         {
  61         case 0:
  62                 return NITIO_G0_Autoincrement_Reg;
  63                 break;
  64         case 1:
  65                 return NITIO_G1_Autoincrement_Reg;
  66                 break;
  67         case 2:
  68                 return NITIO_G2_Autoincrement_Reg;
  69                 break;
  70         case 3:
  71                 return NITIO_G3_Autoincrement_Reg;
  72                 break;
  73         default:
  74                 BUG();
  75                 break;
  76         }
  77         return 0;
  78 }
  79
  80 static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
  81 {
  82         switch(counter_index)
  83         {
  84         case 0:
  85                 return NITIO_G0_Command_Reg;
  86                 break;
  87         case 1:
  88                 return NITIO_G1_Command_Reg;
  89                 break;
  90         case 2:
  91                 return NITIO_G2_Command_Reg;
  92                 break;
  93         case 3:
  94                 return NITIO_G3_Command_Reg;
  95                 break;
  96         default:
  97                 BUG();
  98                 break;
  99         }
 100         return 0;
 101 }
 102
 103 static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned counter_index)
 104 {
 105         switch(counter_index)
 106         {
 107         case 0:
 108                 return NITIO_G0_Counting_Mode_Reg;
 109                 break;
 110         case 1:
 111                 return NITIO_G1_Counting_Mode_Reg;
 112                 break;
 113         case 2:
 114                 return NITIO_G2_Counting_Mode_Reg;
 115                 break;
 116         case 3:
 117                 return NITIO_G3_Counting_Mode_Reg;
 118                 break;
 119         default:
 120                 BUG();
 121                 break;
 122         }
 123         return 0;
 124 }
 125
 126 static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned counter_index)
 127 {
 128         switch(counter_index)
 129         {
 130         case 0:
 131                 return NITIO_G0_Input_Select_Reg;
 132                 break;
 133         case 1:
 134                 return NITIO_G1_Input_Select_Reg;
 135                 break;
 136         case 2:
 137                 return NITIO_G2_Input_Select_Reg;
 138                 break;
 139         case 3:
 140                 return NITIO_G3_Input_Select_Reg;
 141                 break;
 142         default:
 143                 BUG();
 144                 break;
 145         }
 146         return 0;
 147 }
 148
 149 static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned counter_index)
 150 {
 151         switch(counter_index)
 152         {
 153         case 0:
 154         case 1:
 155                 return NITIO_G01_Joint_Reset_Reg;
 156                 break;
 157         case 2:
 158         case 3:
 159                 return NITIO_G23_Joint_Reset_Reg;
 160                 break;
 161         default:
 162                 BUG();
 163                 break;
 164         }
 165         return 0;
 166 }
 167
 168 static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
 169 {
 170         switch(counter_index)
 171         {
 172         case 0:
 173         case 1:
 174                 return NITIO_G01_Status_Reg;
 175                 break;
 176         case 2:
 177         case 3:
 178                 return NITIO_G23_Status_Reg;
 179                 break;
 180         default:
 181                 BUG();
 182                 break;
 183         }
 184         return 0;
 185 }
 186
 187 static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
 188 {
 189         switch(counter_index)
 190         {
 191         case 0:
 192                 return NITIO_G0_LoadA_Reg;
 193                 break;
 194         case 1:
 195                 return NITIO_G1_LoadA_Reg;
 196                 break;
 197         case 2:
 198                 return NITIO_G2_LoadA_Reg;
 199                 break;
 200         case 3:
 201                 return NITIO_G3_LoadA_Reg;
 202                 break;
 203         default:
 204                 BUG();
 205                 break;
 206         }
 207         return 0;
 208 }
 209
 210 static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
 211 {
 212         switch(counter_index)
 213         {
 214         case 0:
 215                 return NITIO_G0_LoadB_Reg;
 216                 break;
 217         case 1:
 218                 return NITIO_G1_LoadB_Reg;
 219                 break;
 220         case 2:
 221                 return NITIO_G2_LoadB_Reg;
 222                 break;
 223         case 3:
 224                 return NITIO_G3_LoadB_Reg;
 225                 break;
 226         default:
 227                 BUG();
 228                 break;
 229         }
 230         return 0;
 231 }
 232
 233 static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
 234 {
 235         switch(counter_index)
 236         {
 237         case 0:
 238                 return NITIO_G0_Mode_Reg;
 239                 break;
 240         case 1:
 241                 return NITIO_G1_Mode_Reg;
 242                 break;
 243         case 2:
 244                 return NITIO_G2_Mode_Reg;
 245                 break;
 246         case 3:
 247                 return NITIO_G3_Mode_Reg;
 248                 break;
 249         default:
 250                 BUG();
 251                 break;
 252         }
 253         return 0;
 254 }
 255
 256 static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
 257 {
 258         switch(counter_index)
 259         {
 260         case 0:
 261                 return NITIO_G0_SW_Save_Reg;
 262                 break;
 263         case 1:
 264                 return NITIO_G1_SW_Save_Reg;
 265                 break;
 266         case 2:
 267                 return NITIO_G2_SW_Save_Reg;
 268                 break;
 269         case 3:
 270                 return NITIO_G3_SW_Save_Reg;
 271                 break;
 272         default:
 273                 BUG();
 274                 break;
 275         }
 276         return 0;
 277 }
 278
 279 static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
 280 {
 281         switch(counter_index)
 282         {
 283         case 0:
 284                 return NITIO_G0_Second_Gate_Reg;
 285                 break;
 286         case 1:
 287                 return NITIO_G1_Second_Gate_Reg;
 288                 break;
 289         case 2:
 290                 return NITIO_G2_Second_Gate_Reg;
 291                 break;
 292         case 3:
 293                 return NITIO_G3_Second_Gate_Reg;
 294                 break;
 295         default:
 296                 BUG();
 297                 break;
 298         }
 299         return 0;
 300 }
 301
 302 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
 303 {
 304         switch(counter_index)
 305         {
 306         case 0:
 307                 return NITIO_G0_DMA_Config_Reg;
 308                 break;
 309         case 1:
 310                 return NITIO_G1_DMA_Config_Reg;
 311                 break;
 312         case 2:
 313                 return NITIO_G2_DMA_Config_Reg;
 314                 break;
 315         case 3:
 316                 return NITIO_G3_DMA_Config_Reg;
 317                 break;
 318         default:
 319                 BUG();
 320                 break;
 321         }
 322         return 0;
 323 }
 324
 325 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
 326 {
 327         switch(counter_index)
 328         {
 329         case 0:
 330                 return NITIO_G0_DMA_Status_Reg;
 331                 break;
 332         case 1:
 333                 return NITIO_G1_DMA_Status_Reg;
 334                 break;
 335         case 2:
 336                 return NITIO_G2_DMA_Status_Reg;
 337                 break;
 338         case 3:
 339                 return NITIO_G3_DMA_Status_Reg;
 340                 break;
 341         default:
 342                 BUG();
 343                 break;
 344         }
 345         return 0;
 346 }
 347
 348 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
 349 {
 350         switch(counter_index)
 351         {
 352         case 0:
 353                 return NITIO_G0_ABZ_Reg;
 354                 break;
 355         case 1:
 356                 return NITIO_G1_ABZ_Reg;
 357                 break;
 358         default:
 359                 BUG();
 360                 break;
 361         }
 362         return 0;
 363 }
 364
 365 enum Gi_Auto_Increment_Reg_Bits
 366 {
 367         Gi_Auto_Increment_Mask = 0xff
 368 };
 369
 370 #define Gi_Up_Down_Shift 5
 371 enum Gi_Command_Reg_Bits
 372 {
 373         Gi_Arm_Bit = 0x1,
 374         Gi_Save_Trace_Bit = 0x2,
 375         Gi_Load_Bit = 0x4,
 376         Gi_Disarm_Bit = 0x10,
 377         Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
 378         Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
 379         Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
 380         Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
 381         Gi_Up_Down_Hardware_Gate_Bits = 0x3  << Gi_Up_Down_Shift,
 382         Gi_Write_Switch_Bit = 0x80,
 383         Gi_Synchronize_Gate_Bit = 0x100,
 384         Gi_Little_Big_Endian_Bit = 0x200,
 385         Gi_Bank_Switch_Start_Bit = 0x400,
 386         Gi_Bank_Switch_Mode_Bit = 0x800,
 387         Gi_Bank_Switch_Enable_Bit = 0x1000,
 388         Gi_Arm_Copy_Bit = 0x2000,
 389         Gi_Save_Trace_Copy_Bit = 0x4000,
 390         Gi_Disarm_Copy_Bit = 0x8000
 391 };
 392
 393 #define Gi_Index_Phase_Bitshift 5
 394 #define Gi_HW_Arm_Select_Shift 8
 395 enum Gi_Counting_Mode_Reg_Bits
 396 {
 397         Gi_Counting_Mode_Mask = 0x7,
 398         Gi_Counting_Mode_Normal_Bits = 0x0,
 399         Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
 400         Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
 401         Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
 402         Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
 403         Gi_Counting_Mode_Sync_Source_Bits = 0x6,
 404         Gi_Index_Mode_Bit = 0x10,
 405         Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
 406         Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
 407         Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
 408         Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
 409         Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
 410         Gi_HW_Arm_Enable_Bit = 0x80, /* from m-series example code, not documented in 660x register level manual */
 411         Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,  /* from m-series example code, not documented in 660x register level manual */
 412         Gi_660x_Prescale_X8_Bit = 0x1000,
 413         Gi_M_Series_Prescale_X8_Bit = 0x2000,
 414         Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
 415         /* must be set for clocks over 40MHz, which includes synchronous counting and quadrature modes */
 416         Gi_660x_Alternate_Sync_Bit = 0x2000,
 417         Gi_M_Series_Alternate_Sync_Bit = 0x4000,
 418         Gi_660x_Prescale_X2_Bit = 0x4000,  /* from m-series example code, not documented in 660x register level manual */
 419         Gi_M_Series_Prescale_X2_Bit = 0x8000,
 420 };
 421 static inline unsigned Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
 422 {
 423         switch(variant)
 424         {
 425         case ni_gpct_variant_e_series:
 426                 return 0;
 427                 break;
 428         case ni_gpct_variant_m_series:
 429                 return Gi_M_Series_Alternate_Sync_Bit;
 430                 break;
 431         case ni_gpct_variant_660x:
 432                 return Gi_660x_Alternate_Sync_Bit;
 433                 break;
 434         default:
 435                 BUG();
 436                 break;
 437         }
 438         return 0;
 439 }
 440 static inline unsigned Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
 441 {
 442         switch(variant)
 443         {
 444         case ni_gpct_variant_e_series:
 445                 return 0;
 446                 break;
 447         case ni_gpct_variant_m_series:
 448                 return Gi_M_Series_Prescale_X2_Bit;
 449                 break;
 450         case ni_gpct_variant_660x:
 451                 return Gi_660x_Prescale_X2_Bit;
 452                 break;
 453         default:
 454                 BUG();
 455                 break;
 456         }
 457         return 0;
 458 }
 459 static inline unsigned Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
 460 {
 461         switch(variant)
 462         {
 463         case ni_gpct_variant_e_series:
 464                 return 0;
 465                 break;
 466         case ni_gpct_variant_m_series:
 467                 return Gi_M_Series_Prescale_X8_Bit;
 468                 break;
 469         case ni_gpct_variant_660x:
 470                 return Gi_660x_Prescale_X8_Bit;
 471                 break;
 472         default:
 473                 BUG();
 474                 break;
 475         }
 476         return 0;
 477 }
 478 static inline unsigned Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
 479 {
 480         switch(variant)
 481         {
 482         case ni_gpct_variant_e_series:
 483                 return 0;
 484                 break;
 485         case ni_gpct_variant_m_series:
 486                 return Gi_M_Series_HW_Arm_Select_Mask;
 487                 break;
 488         case ni_gpct_variant_660x:
 489                 return Gi_660x_HW_Arm_Select_Mask;
 490                 break;
 491         default:
 492                 BUG();
 493                 break;
 494         }
 495         return 0;
 496 }
 497
 498 /* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
 499 enum ni_660x_clock_source
 500 {
 501         NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
 502         NI_660x_Source_Pin_i_Clock = 0x1,
 503         NI_660x_Next_Gate_Clock = 0xa,
 504         NI_660x_Timebase_2_Clock = 0x12,        /* 100KHz */
 505         NI_660x_Next_TC_Clock = 0x13,
 506         NI_660x_Timebase_3_Clock = 0x1e,        /* 80MHz */
 507         NI_660x_Logic_Low_Clock = 0x1f,
 508 };
 509 static const unsigned ni_660x_max_rtsi_channel = 6;
 510 static inline unsigned NI_660x_RTSI_Clock(unsigned n)
 511 {
 512         BUG_ON(n > ni_660x_max_rtsi_channel);
 513         return (0xb + n);
 514 }
 515 static const unsigned ni_660x_max_source_pin = 7;
 516 static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
 517 {
 518         BUG_ON(n > ni_660x_max_source_pin);
 519         return (0x2 + n);
 520 }
 521
 522 /* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
 523 enum ni_m_series_clock_source
 524 {
 525         NI_M_Series_Timebase_1_Clock = 0x0,     /* 20MHz */
 526         NI_M_Series_Timebase_2_Clock = 0x12,    /* 100KHz */
 527         NI_M_Series_Next_TC_Clock = 0x13,
 528         NI_M_Series_Next_Gate_Clock = 0x14,     /* when Gi_Src_SubSelect = 0 */
 529         NI_M_Series_PXI_Star_Trigger_Clock = 0x14,      /* when Gi_Src_SubSelect = 1 */
 530         NI_M_Series_PXI10_Clock = 0x1d,
 531         NI_M_Series_Timebase_3_Clock = 0x1e,    /* 80MHz, when Gi_Src_SubSelect = 0 */
 532         NI_M_Series_Analog_Trigger_Out_Clock = 0x1e,    /* when Gi_Src_SubSelect = 1 */
 533         NI_M_Series_Logic_Low_Clock = 0x1f,
 534 };
 535 static const unsigned ni_m_series_max_pfi_channel = 15;
 536 static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
 537 {
 538         BUG_ON(n > ni_m_series_max_pfi_channel);
 539         if(n < 10) return 1 + n;
 540         else return 0xb + n;
 541 }
 542 static const unsigned ni_m_series_max_rtsi_channel = 7;
 543 static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
 544 {
 545         BUG_ON(n > ni_m_series_max_rtsi_channel);
 546         if(n == 7) return 0x1b;
 547         else return 0xb + n;
 548 }
 549
 550 enum ni_660x_gate_select
 551 {
 552         NI_660x_Source_Pin_i_Gate_Select = 0x0,
 553         NI_660x_Gate_Pin_i_Gate_Select = 0x1,
 554         NI_660x_Next_SRC_Gate_Select = 0xa,
 555         NI_660x_Next_Out_Gate_Select = 0x14,
 556         NI_660x_Logic_Low_Gate_Select = 0x1f,
 557 };
 558 static const unsigned ni_660x_max_gate_pin = 7;
 559 static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
 560 {
 561         BUG_ON(n > ni_660x_max_gate_pin);
 562         return 0x2 + n;
 563 }
 564 static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
 565 {
 566         BUG_ON(n > ni_660x_max_rtsi_channel);
 567         return 0xb + n;
 568 }
 569
 570 enum ni_m_series_gate_select
 571 {
 572         NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
 573         NI_M_Series_AI_START2_Gate_Select = 0x12,
 574         NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
 575         NI_M_Series_Next_Out_Gate_Select = 0x14,
 576         NI_M_Series_AI_START1_Gate_Select = 0x1c,
 577         NI_M_Series_Next_SRC_Gate_Select = 0x1d,
 578         NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
 579         NI_M_Series_Logic_Low_Gate_Select = 0x1f,
 580 };
 581 static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
 582 {
 583         BUG_ON(n > ni_m_series_max_rtsi_channel);
 584         if(n == 7)
 585                 return 0x1b;
 586         return 0xb + n;
 587 }
 588 static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
 589 {
 590         BUG_ON(n > ni_m_series_max_pfi_channel);
 591         if(n < 10)
 592                 return 1 + n;
 593         return 0xb + n;
 594 }
 595
 596 #define Gi_Source_Select_Shift 2
 597 #define Gi_Gate_Select_Shift 7
 598 enum Gi_Input_Select_Bits
 599 {
 600         Gi_Read_Acknowledges_Irq = 0x1, // e-series only
 601         Gi_Write_Acknowledges_Irq = 0x2,        // e-series only
 602         Gi_Source_Select_Mask = 0x7c,
 603         Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
 604         Gi_Gate_Select_Load_Source_Bit = 0x1000,
 605         Gi_Or_Gate_Bit = 0x2000,
 606         Gi_Output_Polarity_Bit = 0x4000,        /* set to invert */
 607         Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
 608 };
 609 static inline unsigned Gi_Source_Select_Bits(unsigned source)
 610 {
 611         return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
 612 }
 613 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
 614 {
 615         return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
 616 }
 617
 618 enum Gi_Mode_Bits
 619 {
 620         Gi_Gating_Mode_Mask = 0x3,
 621         Gi_Gating_Disabled_Bits = 0x0,
 622         Gi_Level_Gating_Bits = 0x1,
 623         Gi_Rising_Edge_Gating_Bits = 0x2,
 624         Gi_Falling_Edge_Gating_Bits = 0x3,
 625         Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with rising edge gating mode */
 626         Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
 627         Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
 628         Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
 629         Gi_Edge_Gate_Starts_Bits = 0x10,
 630         Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
 631         Gi_Stop_Mode_Mask = 0x60,
 632         Gi_Stop_on_Gate_Bits = 0x00,
 633         Gi_Stop_on_Gate_or_TC_Bits = 0x20,
 634         Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
 635         Gi_Load_Source_Select_Bit = 0x80,
 636         Gi_Output_Mode_Mask = 0x300,
 637         Gi_Output_TC_Pulse_Bits = 0x100,
 638         Gi_Output_TC_Toggle_Bits = 0x200,
 639         Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
 640         Gi_Counting_Once_Mask = 0xc00,
 641         Gi_No_Hardware_Disarm_Bits = 0x000,
 642         Gi_Disarm_at_TC_Bits = 0x400,
 643         Gi_Disarm_at_Gate_Bits = 0x800,
 644         Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
 645         Gi_Loading_On_TC_Bit = 0x1000,
 646         Gi_Gate_Polarity_Bit = 0x2000,
 647         Gi_Loading_On_Gate_Bit = 0x4000,
 648         Gi_Reload_Source_Switching_Bit = 0x8000
 649 };
 650
 651 enum ni_660x_second_gate_select
 652 {
 653         NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
 654         NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
 655         NI_660x_Next_SRC_Second_Gate_Select = 0xa,
 656         NI_660x_Next_Out_Second_Gate_Select = 0x14,
 657         NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
 658         NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
 659 };
 660 static const unsigned ni_660x_max_up_down_pin = 7;
 661 static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
 662 {
 663         BUG_ON(n > ni_660x_max_up_down_pin);
 664         return 0x2 + n;
 665 }
 666 static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
 667 {
 668         BUG_ON(n >  ni_660x_max_rtsi_channel);
 669         return 0xb + n;
 670 }
 671
 672 #define Gi_Second_Gate_Select_Shift 7
 673 /*FIXME: m-series has a second gate subselect bit */
 674 /*FIXME: m-series second gate sources are undocumented (by NI)*/
 675 enum Gi_Second_Gate_Bits
 676 {
 677         Gi_Second_Gate_Mode_Bit = 0x1,
 678         Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
 679         Gi_Second_Gate_Polarity_Bit = 0x2000,
 680         Gi_Second_Gate_Subselect_Bit = 0x4000,  /* m-series only */
 681         Gi_Source_Subselect_Bit = 0x8000        /* m-series only */
 682 };
 683 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
 684 {
 685         return (second_gate_select << Gi_Second_Gate_Select_Shift) & Gi_Second_Gate_Select_Mask;
 686 }
 687
 688 enum Gxx_Status_Bits
 689 {
 690         G0_Save_Bit = 0x1,
 691         G1_Save_Bit = 0x2,
 692         G0_Counting_Bit = 0x4,
 693         G1_Counting_Bit = 0x8,
 694         G0_Next_Load_Source_Bit = 0x10,
 695         G1_Next_Load_Source_Bit = 0x20,
 696         G0_Stale_Data_Bit = 0x40,
 697         G1_Stale_Data_Bit = 0x80,
 698         G0_Armed_Bit = 0x100,
 699         G1_Armed_Bit = 0x200,
 700         G0_No_Load_Between_Gates_Bit = 0x400,
 701         G1_No_Load_Between_Gates_Bit = 0x800,
 702         G0_TC_Error_Bit = 0x1000,
 703         G1_TC_Error_Bit = 0x2000
 704 };
 705 static inline unsigned Gi_Counting_Bit(unsigned counter_index)
 706 {
 707         if(counter_index % 2) return G1_Counting_Bit;
 708         return G0_Counting_Bit;
 709 }
 710 static inline unsigned Gi_Armed_Bit(unsigned counter_index)
 711 {
 712         if(counter_index % 2) return G1_Armed_Bit;
 713         return G0_Armed_Bit;
 714 }
 715 static inline unsigned Gi_Next_Load_Source_Bit(unsigned counter_index)
 716 {
 717         if(counter_index % 2) return G1_Next_Load_Source_Bit;
 718         return G0_Next_Load_Source_Bit;
 719 }
 720
 721 /* joint reset register bits */
 722 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
 723 {
 724         return 0x1 << (2 + (counter_index % 2));
 725 }
 726
 727 enum Gi_DMA_Config_Reg_Bits
 728 {
 729         Gi_DMA_Enable_Bit = 0x1,
 730         Gi_DMA_Write_Bit = 0x2,
 731         Gi_DMA_Int_Bit = 0x4
 732 };
 733
 734 static const lsampl_t counter_status_mask = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
 735
 736 static int __init ni_tio_init_module(void)
 737 {
 738         return 0;
 739 }
 740 module_init(ni_tio_init_module);
 741
 742 static void __exit ni_tio_cleanup_module(void)
 743 {
 744 }
 745 module_exit(ni_tio_cleanup_module);
 746
 747 struct ni_gpct_device* ni_gpct_device_construct(comedi_device *dev,
 748         void (*write_register)(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg),
 749         unsigned (*read_register)(struct ni_gpct *counter, enum ni_gpct_register reg),
 750         enum ni_gpct_variant variant, unsigned num_counters)
 751 {
 752         unsigned i;
 753
 754         struct ni_gpct_device *counter_dev = kmalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
 755         if(counter_dev == NULL) return NULL;
 756         counter_dev->dev = dev;
 757         counter_dev->write_register = write_register;
 758         counter_dev->read_register = read_register;
 759         counter_dev->variant = variant;
 760         BUG_ON(num_counters == 0);
 761         counter_dev->counters = kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
 762         if(counter_dev->counters == NULL)
 763         {
 764                 kfree(counter_dev);
 765                 return NULL;
 766         }
 767         for(i = 0; i < num_counters; ++i)
 768         {
 769                 counter_dev->counters[i].counter_dev = counter_dev;
 770         }
 771         counter_dev->num_counters = num_counters;
 772         return counter_dev;
 773 }
 774
 775 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
 776 {
 777         if(counter_dev->counters == NULL) return;
 778         kfree(counter_dev->counters);
 779         kfree(counter_dev);
 780 }
 781
 782 static int ni_tio_counting_mode_registers_present(const struct ni_gpct_device *counter_dev)
 783 {
 784         switch(counter_dev->variant)
 785         {
 786         case ni_gpct_variant_e_series:
 787                 return 0;
 788                 break;
 789         case ni_gpct_variant_m_series:
 790         case ni_gpct_variant_660x:
 791                 return 1;
 792                 break;
 793         default:
 794                 BUG();
 795                 break;
 796         }
 797         return 0;
 798 }
 799
 800 static int ni_tio_second_gate_registers_present(const struct ni_gpct_device *counter_dev)
 801 {
 802         switch(counter_dev->variant)
 803         {
 804         case ni_gpct_variant_e_series:
 805                 return 0;
 806                 break;
 807         case ni_gpct_variant_m_series:
 808         case ni_gpct_variant_660x:
 809                 return 1;
 810                 break;
 811         default:
 812                 BUG();
 813                 break;
 814         }
 815         return 0;
 816 }
 817
 818 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 819 {
 820         counter->counter_dev->write_register(counter, Gi_Reset_Bit(counter->counter_index),
 821                 NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
 822 }
 823
 824 void ni_tio_init_counter(struct ni_gpct *counter)
 825 {
 826         struct ni_gpct_device *counter_dev = counter->counter_dev;
 827
 828         ni_tio_reset_count_and_disarm(counter);
 829         /* initialize counter registers */
 830         counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] = 0x0;
 831         counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
 832                 NITIO_Gi_Autoincrement_Reg(counter->counter_index));
 833         counter_dev->regs[NITIO_Gi_Command_Reg(counter->counter_index)] = Gi_Synchronize_Gate_Bit;
 834         counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_Command_Reg(counter->counter_index)],
 835                 NITIO_Gi_Command_Reg(counter->counter_index));
 836         counter_dev->regs[NITIO_Gi_Mode_Reg(counter->counter_index)] = 0x0;
 837         counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_Mode_Reg(counter->counter_index)],
 838                 NITIO_Gi_Mode_Reg(counter->counter_index));
 839         counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
 840         counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
 841                 NITIO_Gi_LoadA_Reg(counter->counter_index));
 842         counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
 843         counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
 844                 NITIO_Gi_LoadB_Reg(counter->counter_index));
 845         counter_dev->regs[NITIO_Gi_Input_Select_Reg(counter->counter_index)] = 0x0;
 846         counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_Input_Select_Reg(counter->counter_index)],
 847                 NITIO_Gi_Input_Select_Reg(counter->counter_index));
 848         if(ni_tio_counting_mode_registers_present(counter_dev))
 849         {
 850                 counter_dev->regs[NITIO_Gi_Counting_Mode_Reg(counter->counter_index)] = 0x0;
 851                 counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_Counting_Mode_Reg(counter->counter_index)],
 852                         NITIO_Gi_Counting_Mode_Reg(counter->counter_index));
 853         }
 854         if(ni_tio_second_gate_registers_present(counter_dev))
 855         {
 856                 counter_dev->regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] = 0x0;
 857                 counter_dev->write_register(counter, counter_dev->regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)],
 858                         NITIO_Gi_Second_Gate_Reg(counter->counter_index));
 859         }
 860 }
 861
 862 static lsampl_t ni_tio_counter_status(struct ni_gpct *counter)
 863 {
 864         lsampl_t status = 0;
 865         const unsigned bits = counter->counter_dev->read_register(counter, NITIO_Gxx_Status_Reg(counter->counter_index));
 866         if(bits & Gi_Armed_Bit(counter->counter_index))
 867         {
 868                 status |= COMEDI_COUNTER_ARMED;
 869                 if(bits & Gi_Counting_Bit(counter->counter_index))
 870                         status |= COMEDI_COUNTER_COUNTING;
 871         }
 872         return status;
 873 }
 874
 875 static void ni_tio_set_sync_mode(struct ni_gpct *counter,
 876         int force_alt_sync)
 877 {
 878         struct ni_gpct_device *counter_dev = counter->counter_dev;
 879         const unsigned counting_mode_reg = NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
 880         static const uint64_t min_normal_sync_period_ps = 25000;
 881         const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
 882                 ni_tio_generic_clock_src_select(counter));
 883
 884         if(ni_tio_counting_mode_registers_present(counter_dev) == 0) return;
 885
 886         switch(counter_dev->regs[counting_mode_reg] & Gi_Counting_Mode_Mask)
 887         {
 888         case Gi_Counting_Mode_QuadratureX1_Bits:
 889         case Gi_Counting_Mode_QuadratureX2_Bits:
 890         case Gi_Counting_Mode_QuadratureX4_Bits:
 891         case Gi_Counting_Mode_Sync_Source_Bits:
 892                 force_alt_sync = 1;
 893                 break;
 894         default:
 895                 break;
 896         }
 897         /* It's not clear what we should do if clock_period is unknown, so we are not
 898         using the alt sync bit in that case, but allow the caller to decide by using the
 899         force_alt_sync parameter. */
 900         if(force_alt_sync ||
 901                 (clock_period_ps && clock_period_ps < min_normal_sync_period_ps))
 902         {
 903                 counter_dev->regs[counting_mode_reg] |= Gi_Alternate_Sync_Bit(counter_dev->variant);
 904         }else
 905         {
 906                 counter_dev->regs[counting_mode_reg] &= ~Gi_Alternate_Sync_Bit(counter_dev->variant);
 907         }
 908         counter_dev->write_register(counter, counter_dev->regs[counting_mode_reg], counting_mode_reg);
 909 }
 910
 911 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
 912 {
 913         struct ni_gpct_device *counter_dev = counter->counter_dev;
 914
 915         const unsigned counting_mode_reg = NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
 916         const unsigned mode_reg = NITIO_Gi_Mode_Reg(counter->counter_index);
 917         const unsigned command_reg = NITIO_Gi_Command_Reg(counter->counter_index);
 918         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
 919         /* these bits map directly on to the mode register */
 920         static const unsigned mode_reg_direct_mask = NI_GPCT_GATE_ON_BOTH_EDGES_BIT |
 921                 NI_GPCT_EDGE_GATE_MODE_MASK | NI_GPCT_STOP_MODE_MASK |
 922                 NI_GPCT_OUTPUT_MODE_MASK | NI_GPCT_HARDWARE_DISARM_MASK |
 923                 NI_GPCT_LOADING_ON_TC_BIT | NI_GPCT_LOADING_ON_GATE_BIT |
 924                 NI_GPCT_LOAD_B_SELECT_BIT;
 925
 926         switch(mode & NI_GPCT_RELOAD_SOURCE_MASK)
 927         {
 928         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 929                 counter_dev->regs[mode_reg] &= ~Gi_Reload_Source_Switching_Bit;
 930                 counter_dev->regs[input_select_reg] &= ~Gi_Gate_Select_Load_Source_Bit;
 931                 break;
 932         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 933                 counter_dev->regs[mode_reg] |= Gi_Reload_Source_Switching_Bit;
 934                 counter_dev->regs[input_select_reg] &= ~Gi_Gate_Select_Load_Source_Bit;
 935                 break;
 936         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 937                 counter_dev->regs[input_select_reg] |= Gi_Gate_Select_Load_Source_Bit;
 938                 counter_dev->regs[mode_reg] &= ~(Gi_Reload_Source_Switching_Bit | Gi_Gating_Mode_Mask);
 939                 counter_dev->regs[mode_reg] |= Gi_Level_Gating_Bits;
 940                 break;
 941         default:
 942                 break;
 943         }
 944
 945         counter_dev->regs[mode_reg] &= ~mode_reg_direct_mask;
 946         counter_dev->regs[mode_reg] |= mode & mode_reg_direct_mask;
 947         counter_dev->write_register(counter, counter_dev->regs[mode_reg], mode_reg);
 948
 949         if(ni_tio_counting_mode_registers_present(counter_dev))
 950         {
 951                 counter_dev->regs[counting_mode_reg] &= ~Gi_Counting_Mode_Mask;
 952                 counter_dev->regs[counting_mode_reg] |= (mode >> NI_GPCT_COUNTING_MODE_SHIFT) & Gi_Counting_Mode_Mask;
 953                 counter_dev->regs[counting_mode_reg] &= ~Gi_Index_Phase_Mask;
 954                 counter_dev->regs[counting_mode_reg] |= ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) << Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
 955                 if(mode & NI_GPCT_INDEX_ENABLE_BIT)
 956                 {
 957                         counter_dev->regs[counting_mode_reg] |= Gi_Index_Mode_Bit;
 958                 }else
 959                 {
 960                         counter_dev->regs[counting_mode_reg] &= ~Gi_Index_Mode_Bit;
 961                 }
 962                 counter_dev->write_register(counter, counter_dev->regs[counting_mode_reg], counting_mode_reg);
 963                 ni_tio_set_sync_mode(counter, 0);
 964         }
 965
 966         counter_dev->regs[command_reg] &= ~Gi_Up_Down_Mask;
 967         counter_dev->regs[command_reg] |= ((mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) << Gi_Up_Down_Shift) & Gi_Up_Down_Mask;
 968         counter_dev->write_register(counter, counter_dev->regs[command_reg], command_reg);
 969
 970         if(mode & NI_GPCT_OR_GATE_BIT)
 971         {
 972                 counter_dev->regs[input_select_reg] |= Gi_Or_Gate_Bit;
 973         }else
 974         {
 975                 counter_dev->regs[input_select_reg] &= ~Gi_Or_Gate_Bit;
 976         }
 977         if(mode & NI_GPCT_INVERT_OUTPUT_BIT)
 978         {
 979                 counter_dev->regs[input_select_reg] |= Gi_Output_Polarity_Bit;
 980         }else
 981         {
 982                 counter_dev->regs[input_select_reg] &= ~Gi_Output_Polarity_Bit;
 983         }
 984         counter_dev->write_register(counter, counter_dev->regs[input_select_reg], input_select_reg);
 985
 986         return 0;
 987 }
 988
 989 static int ni_tio_arm(struct ni_gpct *counter,
 990         int arm, unsigned start_trigger)
 991 {
 992         struct ni_gpct_device *counter_dev = counter->counter_dev;
 993
 994         unsigned command_bits = counter_dev->regs[NITIO_Gi_Command_Reg(counter->counter_index)];
 995         if(arm)
 996         {
 997                 switch(start_trigger)
 998                 {
 999                 case NI_GPCT_ARM_IMMEDIATE:
1000                         command_bits |= Gi_Arm_Bit;
1001                         break;
1002                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
1003                         command_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
1004                         break;
1005                 default:
1006                         break;
1007                 }
1008                 if(ni_tio_counting_mode_registers_present(counter_dev))
1009                 {
1010                         const unsigned counting_mode_reg = NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
1011                         switch(start_trigger)
1012                         {
1013                         case NI_GPCT_ARM_IMMEDIATE:
1014                         case NI_GPCT_ARM_PAIRED_IMMEDIATE:
1015                                 counter_dev->regs[counting_mode_reg] &= ~Gi_HW_Arm_Enable_Bit;
1016                                 break;
1017                         default:
1018                                 if(start_trigger & NI_GPCT_ARM_UNKNOWN)
1019                                 {
1020                                         /* pass-through the least significant bits so we can figure out what select later */
1021                                         unsigned hw_arm_select_bits;
1022
1023                                         counter_dev->regs[counting_mode_reg] &= ~Gi_HW_Arm_Select_Mask(counter_dev->variant);
1024                                         hw_arm_select_bits = (start_trigger << Gi_HW_Arm_Select_Shift) & Gi_HW_Arm_Select_Mask(counter_dev->variant);
1025                                         counter_dev->regs[counting_mode_reg] |= Gi_HW_Arm_Enable_Bit | hw_arm_select_bits;
1026                                         counter_dev->write_register(counter, counter_dev->regs[counting_mode_reg], counting_mode_reg);
1027                                 }else
1028                                 {
1029                                         return -EINVAL;
1030                                 }
1031                                 break;
1032                         }
1033                 }
1034         }else
1035         {
1036                 command_bits |= Gi_Disarm_Bit;
1037         }
1038         counter_dev->write_register(counter, command_bits, NITIO_Gi_Command_Reg(counter->counter_index));
1039         return 0;
1040 }
1041
1042 static unsigned ni_660x_source_select_bits(lsampl_t clock_source)
1043 {
1044         unsigned ni_660x_clock;
1045         unsigned i;
1046         const unsigned clock_select_bits = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
1047
1048         switch(clock_select_bits)
1049         {
1050         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
1051                 ni_660x_clock = NI_660x_Timebase_1_Clock;
1052                 break;
1053         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
1054                 ni_660x_clock = NI_660x_Timebase_2_Clock;
1055                 break;
1056         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
1057                 ni_660x_clock = NI_660x_Timebase_3_Clock;
1058                 break;
1059         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
1060                 ni_660x_clock = NI_660x_Logic_Low_Clock;
1061                 break;
1062         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
1063                 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
1064                 break;
1065         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
1066                 ni_660x_clock = NI_660x_Next_Gate_Clock;
1067                 break;
1068         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
1069                 ni_660x_clock = NI_660x_Next_TC_Clock;
1070                 break;
1071         default:
1072                 for(i = 0; i <= ni_660x_max_rtsi_channel; ++i)
1073                 {
1074                         if(clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i))
1075                         {
1076                                 ni_660x_clock = NI_660x_RTSI_Clock(i);
1077                                 break;
1078                         }
1079                 }
1080                 if(i <= ni_660x_max_rtsi_channel) break;
1081                 for(i = 0; i <= ni_660x_max_source_pin; ++i)
1082                 {
1083                         if(clock_select_bits == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i))
1084                         {
1085                                 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
1086                                 break;
1087                         }
1088                 }
1089                 if(i <= ni_660x_max_source_pin) break;
1090                 ni_660x_clock = 0;
1091                 BUG();
1092                 break;
1093         }
1094         return Gi_Source_Select_Bits(ni_660x_clock);
1095 }
1096
1097 static unsigned ni_m_series_source_select_bits(lsampl_t clock_source)
1098 {
1099         unsigned ni_m_series_clock;
1100         unsigned i;
1101         const unsigned clock_select_bits = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
1102         switch(clock_select_bits)
1103         {
1104         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
1105                 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
1106                 break;
1107         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
1108                 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
1109                 break;
1110         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
1111                 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
1112                 break;
1113         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
1114                 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
1115                 break;
1116         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
1117                 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
1118                 break;
1119         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
1120                 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
1121                 break;
1122         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
1123                 ni_m_series_clock = NI_M_Series_PXI10_Clock;
1124                 break;
1125         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
1126                 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
1127                 break;
1128         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
1129                 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
1130                 break;
1131         default:
1132                 for(i = 0; i <= ni_m_series_max_rtsi_channel; ++i)
1133                 {
1134                         if(clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i))
1135                         {
1136                                 ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
1137                                 break;
1138                         }
1139                 }
1140                 if(i <= ni_m_series_max_rtsi_channel) break;
1141                 for(i = 0; i <= ni_m_series_max_pfi_channel; ++i)
1142                 {
1143                         if(clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i))
1144                         {
1145                                 ni_m_series_clock = NI_M_Series_PFI_Clock(i);
1146                                 break;
1147                         }
1148                 }
1149                 if(i <= ni_m_series_max_pfi_channel) break;
1150                 rt_printk("invalid clock source 0x%lx\n", (unsigned long)clock_source);
1151                 BUG();
1152                 ni_m_series_clock = 0;
1153                 break;
1154         }
1155         return Gi_Source_Select_Bits(ni_m_series_clock);
1156 };
1157
1158 static void ni_tio_set_source_subselect(struct ni_gpct *counter, lsampl_t clock_source)
1159 {
1160         struct ni_gpct_device *counter_dev = counter->counter_dev;
1161         const unsigned second_gate_reg = NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1162
1163         if(counter_dev->variant != ni_gpct_variant_m_series) return;
1164         switch(clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK)
1165         {
1166         /* Gi_Source_Subselect is zero */
1167         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
1168         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
1169                 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
1170                 break;
1171         /* Gi_Source_Subselect is one */
1172         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
1173         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
1174                 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
1175                 break;
1176         /* Gi_Source_Subselect doesn't matter */
1177         default:
1178                 return;
1179                 break;
1180         }
1181         counter_dev->write_register(counter, counter_dev->regs[second_gate_reg], second_gate_reg);
1182 }
1183
1184 static int ni_tio_set_clock_src(struct ni_gpct *counter,
1185         lsampl_t clock_source, lsampl_t period_ns)
1186 {
1187         struct ni_gpct_device *counter_dev = counter->counter_dev;
1188         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1189         static const uint64_t pico_per_nano = 1000;
1190
1191 /*FIXME: validate clock source */
1192         counter_dev->regs[input_select_reg] &= ~Gi_Source_Select_Mask;
1193         switch(counter_dev->variant)
1194         {
1195         case ni_gpct_variant_660x:
1196                 counter_dev->regs[input_select_reg] |= ni_660x_source_select_bits(clock_source);
1197                 break;
1198         case ni_gpct_variant_e_series:
1199         case ni_gpct_variant_m_series:
1200                 counter_dev->regs[input_select_reg] |= ni_m_series_source_select_bits(clock_source);
1201                 break;
1202         default:
1203                 BUG();
1204                 break;
1205         }
1206         if(clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
1207                 counter_dev->regs[input_select_reg] |= Gi_Source_Polarity_Bit;
1208         else
1209                 counter_dev->regs[input_select_reg] &= ~Gi_Source_Polarity_Bit;
1210         counter_dev->write_register(counter, counter_dev->regs[input_select_reg], input_select_reg);
1211         ni_tio_set_source_subselect(counter, clock_source);
1212         if(ni_tio_counting_mode_registers_present(counter_dev))
1213         {
1214                 const unsigned counting_mode_reg = NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
1215                 const unsigned prescaling_mode = clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
1216
1217                 switch(prescaling_mode)
1218                 {
1219                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
1220                         counter_dev->regs[counting_mode_reg] &= ~(Gi_Prescale_X2_Bit(counter_dev->variant) | Gi_Prescale_X8_Bit(counter_dev->variant));
1221                         break;
1222                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
1223                         counter_dev->regs[counting_mode_reg] |= Gi_Prescale_X2_Bit(counter_dev->variant);
1224                         counter_dev->regs[counting_mode_reg] &= ~Gi_Prescale_X8_Bit(counter_dev->variant);
1225                         break;
1226                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
1227                         counter_dev->regs[counting_mode_reg] |= Gi_Prescale_X8_Bit(counter_dev->variant);
1228                         counter_dev->regs[counting_mode_reg] &= ~Gi_Prescale_X2_Bit(counter_dev->variant);
1229                         break;
1230                 default:
1231                         return -EINVAL;
1232                         break;
1233                 }
1234                 counter_dev->write_register(counter, counter_dev->regs[counting_mode_reg], counting_mode_reg);
1235         }
1236         counter->clock_period_ps = pico_per_nano * period_ns;
1237         ni_tio_set_sync_mode(counter, 0);
1238         return 0;
1239 }
1240
1241 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
1242 {
1243         struct ni_gpct_device *counter_dev = counter->counter_dev;
1244         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1245         const unsigned counting_mode_reg = NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
1246         unsigned bits = 0;
1247
1248         if(counter_dev->regs[input_select_reg] & Gi_Source_Polarity_Bit)
1249                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
1250         if(counter_dev->regs[counting_mode_reg] & Gi_Prescale_X2_Bit(counter_dev->variant))
1251                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
1252         if(counter_dev->regs[counting_mode_reg] & Gi_Prescale_X8_Bit(counter_dev->variant))
1253                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
1254         return bits;
1255 }
1256
1257 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
1258 {
1259         struct ni_gpct_device *counter_dev = counter->counter_dev;
1260         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1261         const unsigned second_gate_reg = NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1262         unsigned clock_source = 0;
1263         unsigned i;
1264         const unsigned input_select = (counter_dev->regs[input_select_reg] & Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
1265
1266         switch(input_select)
1267         {
1268         case NI_M_Series_Timebase_1_Clock:
1269                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
1270                 break;
1271         case NI_M_Series_Timebase_2_Clock:
1272                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
1273                 break;
1274         case NI_M_Series_Timebase_3_Clock:
1275                 if(counter_dev->regs[second_gate_reg] & Gi_Source_Subselect_Bit)
1276                         clock_source = NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
1277                 else
1278                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
1279                 break;
1280         case NI_M_Series_Logic_Low_Clock:
1281                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
1282                 break;
1283         case NI_M_Series_Next_Gate_Clock:
1284                 if(counter_dev->regs[second_gate_reg] & Gi_Source_Subselect_Bit)
1285                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
1286                 else
1287                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
1288                 break;
1289         case NI_M_Series_PXI10_Clock:
1290                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
1291                 break;
1292         case NI_M_Series_Next_TC_Clock:
1293                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
1294                 break;
1295         default:
1296                 for(i = 0; i <= ni_m_series_max_rtsi_channel; ++i)
1297                 {
1298                         if(input_select == NI_M_Series_RTSI_Clock(i))
1299                         {
1300                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
1301                                 break;
1302                         }
1303                 }
1304                 if(i <= ni_m_series_max_rtsi_channel) break;
1305                 for(i = 0; i <= ni_m_series_max_pfi_channel; ++i)
1306                 {
1307                         if(input_select == NI_M_Series_PFI_Clock(i))
1308                         {
1309                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
1310                                 break;
1311                         }
1312                 }
1313                 if(i <= ni_m_series_max_pfi_channel) break;
1314                 BUG();
1315                 break;
1316         }
1317         clock_source |= ni_tio_clock_src_modifiers(counter);
1318         return clock_source;
1319 }
1320
1321 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
1322 {
1323         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1324         unsigned clock_source = 0;
1325         unsigned i;
1326         const unsigned input_select = (counter->counter_dev->regs[input_select_reg] & Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
1327
1328         switch(input_select)
1329         {
1330         case NI_660x_Timebase_1_Clock:
1331                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
1332                 break;
1333         case NI_660x_Timebase_2_Clock:
1334                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
1335                 break;
1336         case NI_660x_Timebase_3_Clock:
1337                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
1338                 break;
1339         case NI_660x_Logic_Low_Clock:
1340                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
1341                 break;
1342         case NI_660x_Source_Pin_i_Clock:
1343                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
1344                 break;
1345         case NI_660x_Next_Gate_Clock:
1346                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
1347                 break;
1348         case NI_660x_Next_TC_Clock:
1349                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
1350                 break;
1351         default:
1352                 for(i = 0; i <= ni_660x_max_rtsi_channel; ++i)
1353                 {
1354                         if(input_select == NI_660x_RTSI_Clock(i))
1355                         {
1356                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
1357                                 break;
1358                         }
1359                 }
1360                 if(i <= ni_660x_max_rtsi_channel) break;
1361                 for(i = 0; i <= ni_660x_max_source_pin; ++i)
1362                 {
1363                         if(input_select == NI_660x_Source_Pin_Clock(i))
1364                         {
1365                                 clock_source = NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
1366                                 break;
1367                         }
1368                 }
1369                 if(i <= ni_660x_max_source_pin) break;
1370                 BUG();
1371                 break;
1372         }
1373         clock_source |= ni_tio_clock_src_modifiers(counter);
1374         return clock_source;
1375 }
1376
1377 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
1378 {
1379         switch(counter->counter_dev->variant)
1380         {
1381         case ni_gpct_variant_e_series:
1382         case ni_gpct_variant_m_series:
1383                 return ni_m_series_clock_src_select(counter);
1384                 break;
1385         case ni_gpct_variant_660x:
1386                 return ni_660x_clock_src_select(counter);
1387                 break;
1388         default:
1389                 BUG();
1390                 break;
1391         }
1392         return 0;
1393 }
1394
1395 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter, unsigned generic_clock_source)
1396 {
1397         uint64_t clock_period_ps;
1398
1399         switch(generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK)
1400         {
1401         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
1402                 clock_period_ps = 50000;
1403                 break;
1404         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
1405                 clock_period_ps = 10000000;
1406                 break;
1407         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
1408                 clock_period_ps = 12500;
1409                 break;
1410         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
1411                 clock_period_ps = 100000;
1412                 break;
1413         default:
1414                 /* clock period is specified by user with prescaling already taken into account. */
1415                 return counter->clock_period_ps;
1416                 break;
1417         }
1418
1419         switch(generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK)
1420         {
1421         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
1422                 break;
1423         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
1424                 clock_period_ps *= 2;
1425                 break;
1426         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
1427                 clock_period_ps *= 8;
1428                 break;
1429         default:
1430                 BUG();
1431                 break;
1432         }
1433         return clock_period_ps;
1434 }
1435
1436 static void ni_tio_get_clock_src(struct ni_gpct *counter,
1437         lsampl_t *clock_source, lsampl_t *period_ns)
1438 {
1439         static const unsigned pico_per_nano = 1000;
1440         uint64_t temp64;
1441         *clock_source = ni_tio_generic_clock_src_select(counter);
1442         temp64 = ni_tio_clock_period_ps(counter, *clock_source);
1443         do_div(temp64, pico_per_nano);
1444         *period_ns = temp64;
1445 }
1446
1447 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter, lsampl_t gate_source)
1448 {
1449         struct ni_gpct_device *counter_dev = counter->counter_dev;
1450         const unsigned mode_reg = NITIO_Gi_Mode_Reg(counter->counter_index);
1451
1452         if(gate_source & CR_INVERT)
1453         {
1454                 counter_dev->regs[mode_reg] |= Gi_Gate_Polarity_Bit;
1455         }else
1456         {
1457                 counter_dev->regs[mode_reg] &= ~Gi_Gate_Polarity_Bit;
1458         }
1459         counter_dev->regs[mode_reg] &= ~Gi_Gating_Mode_Mask;
1460         if(gate_source & CR_EDGE)
1461         {
1462                 counter_dev->regs[mode_reg] |= Gi_Rising_Edge_Gating_Bits;
1463         }else
1464         {
1465                 counter_dev->regs[mode_reg] |= Gi_Level_Gating_Bits;
1466         }
1467         counter_dev->write_register(counter, counter_dev->regs[mode_reg], mode_reg);
1468 }
1469
1470 static int ni_660x_set_first_gate(struct ni_gpct *counter, lsampl_t gate_source)
1471 {
1472         struct ni_gpct_device *counter_dev = counter->counter_dev;
1473         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1474         const unsigned selected_gate = CR_CHAN(gate_source);
1475         /* bits of selected_gate that may be meaningful to input select register */
1476         const unsigned selected_gate_mask = 0x1f;
1477         unsigned ni_660x_gate_select;
1478         unsigned i;
1479
1480         switch(selected_gate)
1481         {
1482         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1483                 ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
1484                 break;
1485         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1486         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1487         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1488         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
1489                 ni_660x_gate_select = selected_gate & selected_gate_mask;
1490                 break;
1491         default:
1492                 for(i = 0; i <= ni_660x_max_rtsi_channel; ++i)
1493                 {
1494                         if(selected_gate == NI_GPCT_RTSI_GATE_SELECT(i))
1495                         {
1496                                 ni_660x_gate_select = selected_gate & selected_gate_mask;
1497                                 break;
1498                         }
1499                 }
1500                 if(i <= ni_660x_max_rtsi_channel) break;
1501                 for(i = 0; i <= ni_660x_max_gate_pin; ++i)
1502                 {
1503                         if(selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i))
1504                         {
1505                                 ni_660x_gate_select = selected_gate & selected_gate_mask;
1506                                 break;
1507                         }
1508                 }
1509                 if(i <= ni_660x_max_gate_pin) break;
1510                 return -EINVAL;
1511                 break;
1512         }
1513         counter_dev->regs[input_select_reg] &= ~Gi_Gate_Select_Mask;
1514         counter_dev->regs[input_select_reg] |= Gi_Gate_Select_Bits(ni_660x_gate_select);
1515         counter_dev->write_register(counter, counter_dev->regs[input_select_reg], input_select_reg);
1516         return 0;
1517 }
1518
1519 static int ni_m_series_set_first_gate(struct ni_gpct *counter, lsampl_t gate_source)
1520 {
1521         struct ni_gpct_device *counter_dev = counter->counter_dev;
1522         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1523         const unsigned selected_gate = CR_CHAN(gate_source);
1524         /* bits of selected_gate that may be meaningful to input select register */
1525         const unsigned selected_gate_mask = 0x1f;
1526         unsigned ni_m_series_gate_select;
1527         unsigned i;
1528
1529         switch(selected_gate)
1530         {
1531         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
1532         case NI_GPCT_AI_START2_GATE_SELECT:
1533         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
1534         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1535         case NI_GPCT_AI_START1_GATE_SELECT:
1536         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1537         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1538         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1539                 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1540                 break;
1541         default:
1542                 for(i = 0; i <= ni_m_series_max_rtsi_channel; ++i)
1543                 {
1544                         if(selected_gate == NI_GPCT_RTSI_GATE_SELECT(i))
1545                         {
1546                                 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1547                                 break;
1548                         }
1549                 }
1550                 if(i <= ni_m_series_max_rtsi_channel) break;
1551                 for(i = 0; i <= ni_m_series_max_pfi_channel; ++i)
1552                 {
1553                         if(selected_gate == NI_GPCT_PFI_GATE_SELECT(i))
1554                         {
1555                                 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1556                                 break;
1557                         }
1558                 }
1559                 if(i <= ni_m_series_max_pfi_channel) break;
1560                 return -EINVAL;
1561                 break;
1562         }
1563         counter_dev->regs[input_select_reg] &= ~Gi_Gate_Select_Mask;
1564         counter_dev->regs[input_select_reg] |= Gi_Gate_Select_Bits(ni_m_series_gate_select);
1565         counter_dev->write_register(counter, counter_dev->regs[input_select_reg], input_select_reg);
1566         return 0;
1567 }
1568
1569 static int ni_660x_set_second_gate(struct ni_gpct *counter, lsampl_t gate_source)
1570 {
1571         struct ni_gpct_device *counter_dev = counter->counter_dev;
1572         const unsigned second_gate_reg = NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1573         const unsigned selected_second_gate = CR_CHAN(gate_source);
1574         /* bits of second_gate that may be meaningful to second gate register */
1575         static const unsigned selected_second_gate_mask = 0x1f;
1576         unsigned ni_660x_second_gate_select;
1577         unsigned i;
1578
1579         switch(selected_second_gate)
1580         {
1581         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1582         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1583         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1584         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1585         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1586                 ni_660x_second_gate_select = selected_second_gate & selected_second_gate_mask;
1587                 break;
1588         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1589                 ni_660x_second_gate_select = NI_660x_Next_SRC_Second_Gate_Select;
1590                 break;
1591         default:
1592                 for(i = 0; i <= ni_660x_max_rtsi_channel; ++i)
1593                 {
1594                         if(selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i))
1595                         {
1596                                 ni_660x_second_gate_select = selected_second_gate & selected_second_gate_mask;
1597                                 break;
1598                         }
1599                 }
1600                 if(i <= ni_660x_max_rtsi_channel) break;
1601                 for(i = 0; i <= ni_660x_max_up_down_pin; ++i)
1602                 {
1603                         if(selected_second_gate == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i))
1604                         {
1605                                 ni_660x_second_gate_select = selected_second_gate & selected_second_gate_mask;
1606                                 break;
1607                         }
1608                 }
1609                 if(i <= ni_660x_max_up_down_pin) break;
1610                 return -EINVAL;
1611                 break;
1612         };
1613         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1614         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1615         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
1616         counter_dev->write_register(counter, counter_dev->regs[second_gate_reg], second_gate_reg);
1617         return 0;
1618 }
1619
1620 static int ni_m_series_set_second_gate(struct ni_gpct *counter, lsampl_t gate_source)
1621 {
1622         struct ni_gpct_device *counter_dev = counter->counter_dev;
1623         const unsigned second_gate_reg = NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1624         const unsigned selected_second_gate = CR_CHAN(gate_source);
1625         /* bits of second_gate that may be meaningful to second gate register */
1626         static const unsigned selected_second_gate_mask = 0x1f;
1627         unsigned ni_m_series_second_gate_select;
1628
1629         /* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
1630         the bits through for now. */
1631         switch(selected_second_gate)
1632         {
1633         default:
1634                 ni_m_series_second_gate_select = selected_second_gate & selected_second_gate_mask;
1635                 break;
1636         };
1637         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1638         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1639         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
1640         counter_dev->write_register(counter, counter_dev->regs[second_gate_reg], second_gate_reg);
1641         return 0;
1642 }
1643
1644 static int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, lsampl_t gate_source)
1645 {
1646         struct ni_gpct_device *counter_dev = counter->counter_dev;
1647         const unsigned mode_reg = NITIO_Gi_Mode_Reg(counter->counter_index);
1648         const unsigned second_gate_reg = NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1649
1650         switch(gate_index)
1651         {
1652         case 0:
1653                 if(CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT)
1654                 {
1655                         counter_dev->regs[mode_reg] &= ~Gi_Gating_Mode_Mask;
1656                         counter_dev->regs[mode_reg] |= Gi_Gating_Disabled_Bits;
1657                         counter_dev->write_register(counter, counter_dev->regs[mode_reg], mode_reg);
1658                         return 0;
1659                 }
1660                 ni_tio_set_first_gate_modifiers(counter, gate_source);
1661                 switch(counter_dev->variant)
1662                 {
1663                 case ni_gpct_variant_e_series:
1664                 case ni_gpct_variant_m_series:
1665                         return ni_m_series_set_first_gate(counter, gate_source);
1666                         break;
1667                 case ni_gpct_variant_660x:
1668                         return ni_660x_set_first_gate(counter, gate_source);
1669                         break;
1670                 default:
1671                         BUG();
1672                         break;
1673                 }
1674                 break;
1675         case 1:
1676                 if(ni_tio_second_gate_registers_present(counter_dev) == 0) return -EINVAL;
1677                 if(CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT)
1678                 {
1679                         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Mode_Bit;
1680                         counter_dev->write_register(counter, counter_dev->regs[second_gate_reg], second_gate_reg);
1681                         return 0;
1682                 }
1683                 if(gate_source & CR_INVERT)
1684                 {
1685                         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Polarity_Bit;
1686                 }else
1687                 {
1688                         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Polarity_Bit;
1689                 }
1690                 switch(counter_dev->variant)
1691                 {
1692                 case ni_gpct_variant_m_series:
1693                         return ni_m_series_set_second_gate(counter, gate_source);
1694                         break;
1695                 case ni_gpct_variant_660x:
1696                         return ni_660x_set_second_gate(counter, gate_source);
1697                         break;
1698                 default:
1699                         BUG();
1700                         break;
1701                 }
1702                 break;
1703         default:
1704                 return -EINVAL;
1705                 break;
1706         }
1707         return 0;
1708 }
1709
1710 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index, lsampl_t source)
1711 {
1712         struct ni_gpct_device *counter_dev = counter->counter_dev;
1713
1714         if(counter_dev->variant == ni_gpct_variant_m_series)
1715         {
1716                 unsigned int abz_reg, shift, mask;
1717
1718                 abz_reg = NITIO_Gi_ABZ_Reg(counter->counter_index);
1719                 switch(index) {
1720                 case NI_GPCT_SOURCE_ENCODER_A:
1721                         shift = 10;
1722                         break;
1723                 case NI_GPCT_SOURCE_ENCODER_B:
1724                         shift = 5;
1725                         break;
1726                 case NI_GPCT_SOURCE_ENCODER_Z:
1727                         shift = 0;
1728                         break;
1729                 default:
1730                         return -EINVAL;
1731                         break;
1732                 }
1733                 mask = 0x1f << shift;
1734                 if(source > 0x1f)
1735                 {
1736                         /* Disable gate */
1737                         source = 0x1f;
1738                 }
1739                 counter_dev->regs[abz_reg] &= ~mask;
1740                 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1741                 counter_dev->write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1742 //              rt_printk("%s %x %d %d\n", __FUNCTION__, counter_dev->regs[abz_reg], index, source);
1743                 return 0;
1744         }
1745         return -EINVAL;
1746 }
1747
1748 static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned ni_660x_gate_select)
1749 {
1750         unsigned i;
1751
1752         switch(ni_660x_gate_select)
1753         {
1754         case NI_660x_Source_Pin_i_Gate_Select:
1755                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1756                 break;
1757         case NI_660x_Gate_Pin_i_Gate_Select:
1758                 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1759                 break;
1760         case NI_660x_Next_SRC_Gate_Select:
1761                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1762                 break;
1763         case NI_660x_Next_Out_Gate_Select:
1764                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1765                 break;
1766         case NI_660x_Logic_Low_Gate_Select:
1767                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1768                 break;
1769         default:
1770                 for(i = 0; i <= ni_660x_max_rtsi_channel; ++i)
1771                 {
1772                         if(ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i))
1773                         {
1774                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1775                                 break;
1776                         }
1777                 }
1778                 if(i <= ni_660x_max_rtsi_channel) break;
1779                 for(i = 0; i <= ni_660x_max_gate_pin; ++i)
1780                 {
1781                         if(ni_660x_gate_select == NI_660x_Gate_Pin_Gate_Select(i))
1782                         {
1783                                 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1784                                 break;
1785                         }
1786                 }
1787                 if(i <= ni_660x_max_gate_pin) break;
1788                 BUG();
1789                 break;
1790         }
1791         return 0;
1792 };
1793
1794 static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned ni_m_series_gate_select)
1795 {
1796         unsigned i;
1797
1798         switch(ni_m_series_gate_select)
1799         {
1800         case NI_M_Series_Timestamp_Mux_Gate_Select:
1801                 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1802                 break;
1803         case NI_M_Series_AI_START2_Gate_Select:
1804                 return NI_GPCT_AI_START2_GATE_SELECT;
1805                 break;
1806         case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1807                 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1808                 break;
1809         case NI_M_Series_Next_Out_Gate_Select:
1810                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1811                 break;
1812         case NI_M_Series_AI_START1_Gate_Select:
1813                 return NI_GPCT_AI_START1_GATE_SELECT;
1814                 break;
1815         case NI_M_Series_Next_SRC_Gate_Select:
1816                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1817                 break;
1818         case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1819                 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1820                 break;
1821         case NI_M_Series_Logic_Low_Gate_Select:
1822                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1823                 break;
1824         default:
1825                 for(i = 0; i <= ni_m_series_max_rtsi_channel; ++i)
1826                 {
1827                         if(ni_m_series_gate_select == NI_M_Series_RTSI_Gate_Select(i))
1828                         {
1829                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1830                                 break;
1831                         }
1832                 }
1833                 if(i <= ni_m_series_max_rtsi_channel) break;
1834                 for(i = 0; i <= ni_m_series_max_pfi_channel; ++i)
1835                 {
1836                         if(ni_m_series_gate_select == NI_M_Series_PFI_Gate_Select(i))
1837                         {
1838                                 return NI_GPCT_PFI_GATE_SELECT(i);
1839                                 break;
1840                         }
1841                 }
1842                 if(i <= ni_m_series_max_pfi_channel) break;
1843                 BUG();
1844                 break;
1845         }
1846         return 0;
1847 };
1848
1849 static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned ni_660x_gate_select)
1850 {
1851         unsigned i;
1852
1853         switch(ni_660x_gate_select)
1854         {
1855         case NI_660x_Source_Pin_i_Second_Gate_Select:
1856                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1857                 break;
1858         case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1859                 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1860                 break;
1861         case NI_660x_Next_SRC_Second_Gate_Select:
1862                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1863                 break;
1864         case NI_660x_Next_Out_Second_Gate_Select:
1865                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1866                 break;
1867         case NI_660x_Selected_Gate_Second_Gate_Select:
1868                 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1869                 break;
1870         case NI_660x_Logic_Low_Second_Gate_Select:
1871                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1872                 break;
1873         default:
1874                 for(i = 0; i <= ni_660x_max_rtsi_channel; ++i)
1875                 {
1876                         if(ni_660x_gate_select == NI_660x_RTSI_Second_Gate_Select(i))
1877                         {
1878                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1879                                 break;
1880                         }
1881                 }
1882                 if(i <= ni_660x_max_rtsi_channel) break;
1883                 for(i = 0; i <= ni_660x_max_up_down_pin; ++i)
1884                 {
1885                         if(ni_660x_gate_select == NI_660x_Up_Down_Pin_Second_Gate_Select(i))
1886                         {
1887                                 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1888                                 break;
1889                         }
1890                 }
1891                 if(i <= ni_660x_max_up_down_pin) break;
1892                 BUG();
1893                 break;
1894         }
1895         return 0;
1896 };
1897
1898 static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned ni_m_series_gate_select)
1899 {
1900         /*FIXME: the second gate sources for the m series are undocumented, so we just return
1901         * the raw bits for now. */
1902         switch(ni_m_series_gate_select)
1903         {
1904         default:
1905                 return ni_m_series_gate_select;
1906                 break;
1907         }
1908         return 0;
1909 };
1910
1911 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index, lsampl_t *gate_source)
1912 {
1913         struct ni_gpct_device *counter_dev = counter->counter_dev;
1914         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
1915         const unsigned mode_reg = NITIO_Gi_Mode_Reg(counter->counter_index);
1916         const unsigned second_gate_reg = NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1917         unsigned gate_select_bits;
1918
1919         switch(gate_index)
1920         {
1921         case 0:
1922                 if((counter_dev->regs[mode_reg] & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits)
1923                 {
1924                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1925                         return 0;
1926                 }else
1927                 {
1928                         gate_select_bits = (counter_dev->regs[input_select_reg] & Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1929                 }
1930                 switch(counter_dev->variant)
1931                 {
1932                 case ni_gpct_variant_e_series:
1933                 case ni_gpct_variant_m_series:
1934                         *gate_source = ni_m_series_first_gate_to_generic_gate_source(gate_select_bits);
1935                         break;
1936                 case ni_gpct_variant_660x:
1937                         *gate_source = ni_660x_first_gate_to_generic_gate_source(gate_select_bits);
1938                         break;
1939                 default:
1940                         BUG();
1941                         break;
1942                 }
1943                 if(counter_dev->regs[mode_reg] & Gi_Gate_Polarity_Bit)
1944                 {
1945                         *gate_source |= CR_INVERT;
1946                 }
1947                 if((counter_dev->regs[mode_reg] & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1948                 {
1949                         *gate_source |= CR_EDGE;
1950                 }
1951                 break;
1952         case 1:
1953                 if((counter_dev->regs[mode_reg] & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits ||
1954                         (counter_dev->regs[second_gate_reg] & Gi_Second_Gate_Mode_Bit) == 0)
1955                 {
1956                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1957                         return 0;
1958                 }else
1959                 {
1960                         gate_select_bits = (counter_dev->regs[second_gate_reg] & Gi_Second_Gate_Select_Mask) >> Gi_Second_Gate_Select_Shift;
1961                 }
1962                 switch(counter_dev->variant)
1963                 {
1964                 case ni_gpct_variant_e_series:
1965                 case ni_gpct_variant_m_series:
1966                         *gate_source = ni_m_series_second_gate_to_generic_gate_source(gate_select_bits);
1967                         break;
1968                 case ni_gpct_variant_660x:
1969                         *gate_source = ni_660x_second_gate_to_generic_gate_source(gate_select_bits);
1970                         break;
1971                 default:
1972                         BUG();
1973                         break;
1974                 }
1975                 if(counter_dev->regs[second_gate_reg] & Gi_Second_Gate_Polarity_Bit)
1976                 {
1977                         *gate_source |= CR_INVERT;
1978                 }
1979                 /* second gate can't have edge/level mode set independently */
1980                 if((counter_dev->regs[mode_reg] & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1981                 {
1982                         *gate_source |= CR_EDGE;
1983                 }
1984                 break;
1985         default:
1986                 return -EINVAL;
1987                 break;
1988         }
1989         return 0;
1990 }
1991
1992 int ni_tio_insn_config(struct ni_gpct *counter,
1993         comedi_insn *insn, lsampl_t *data)
1994 {
1995         switch(data[0])
1996         {
1997         case INSN_CONFIG_SET_COUNTER_MODE:
1998                 return ni_tio_set_counter_mode(counter, data[1]);
1999                 break;
2000         case INSN_CONFIG_ARM:
2001                 return ni_tio_arm(counter, 1, data[1]);
2002                 break;
2003         case INSN_CONFIG_DISARM:
2004                 ni_tio_arm(counter, 0, 0);
2005                 return 0;
2006                 break;
2007         case INSN_CONFIG_GET_COUNTER_STATUS:
2008                 data[1] = ni_tio_counter_status(counter);
2009                 data[2] = counter_status_mask;
2010                 return 0;
2011                 break;
2012         case INSN_CONFIG_SET_CLOCK_SRC:
2013                 return ni_tio_set_clock_src(counter, data[1], data[2]);
2014                 break;
2015         case INSN_CONFIG_GET_CLOCK_SRC:
2016                 ni_tio_get_clock_src(counter, &data[1], &data[2]);
2017                 return 0;
2018                 break;
2019         case INSN_CONFIG_SET_GATE_SRC:
2020                 return ni_tio_set_gate_src(counter, data[1], data[2]);
2021                 break;
2022         case INSN_CONFIG_GET_GATE_SRC:
2023                 return ni_tio_get_gate_src(counter, data[1], &data[2]);
2024                 break;
2025         case INSN_CONFIG_SET_OTHER_SRC:
2026                 return ni_tio_set_other_src(counter, data[1], data[2]);
2027                 break;
2028         case INSN_CONFIG_RESET:
2029                 ni_tio_reset_count_and_disarm(counter);
2030                 return 0;
2031                 break;
2032         default:
2033                 break;
2034         }
2035         return -EINVAL;
2036 }
2037
2038 int ni_tio_rinsn(struct ni_gpct *counter,
2039         comedi_insn *insn, lsampl_t *data)
2040 {
2041         struct ni_gpct_device *counter_dev = counter->counter_dev;
2042         const unsigned command_reg = NITIO_Gi_Command_Reg(counter->counter_index);
2043         const unsigned channel = CR_CHAN(insn->chanspec);
2044         unsigned first_read;
2045         unsigned second_read;
2046         unsigned correct_read;
2047
2048         if(insn->n < 1) return 0;
2049         switch(channel)
2050         {
2051         case 0:
2052                 counter_dev->regs[command_reg] &= ~Gi_Save_Trace_Bit;
2053                 counter_dev->write_register(counter, counter_dev->regs[command_reg], command_reg);
2054                 counter_dev->write_register(counter, counter_dev->regs[command_reg] | Gi_Save_Trace_Bit,
2055                         command_reg);
2056                 /* The count doesn't get latched until the next clock edge, so it is possible the count
2057                 may change (once) while we are reading.  Since the read of the SW_Save_Reg isn't
2058                 atomic (apparently even when it's a 32 bit register according to 660x docs),
2059                 we need to read twice and make sure the reading hasn't changed.  If it has,
2060                 a third read will be correct since the count value will definitely have latched by then. */
2061                 first_read = counter_dev->read_register(counter, NITIO_Gi_SW_Save_Reg(counter->counter_index));
2062                 second_read = counter_dev->read_register(counter, NITIO_Gi_SW_Save_Reg(counter->counter_index));
2063                 if(first_read != second_read)
2064                         correct_read = counter_dev->read_register(counter, NITIO_Gi_SW_Save_Reg(counter->counter_index));
2065                 else
2066                         correct_read = first_read;
2067                 data[0] = correct_read;
2068                 return 0;
2069                 break;
2070         case 1:
2071                 data[0] = counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
2072                 break;
2073         case 2:
2074                 data[0] = counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
2075                 break;
2076         };
2077         return 0;
2078 }
2079
2080 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
2081 {
2082         const unsigned bits = counter->counter_dev->read_register(counter, NITIO_Gxx_Status_Reg(counter->counter_index));
2083
2084         if(bits & Gi_Next_Load_Source_Bit(counter->counter_index))
2085         {
2086                 return NITIO_Gi_LoadB_Reg(counter->counter_index);
2087         }else
2088         {
2089                 return NITIO_Gi_LoadA_Reg(counter->counter_index);
2090         }
2091 }
2092
2093 int ni_tio_winsn(struct ni_gpct *counter,
2094         comedi_insn *insn,
2095         lsampl_t * data)
2096 {
2097         struct ni_gpct_device *counter_dev = counter->counter_dev;
2098         const unsigned channel = CR_CHAN(insn->chanspec);
2099         const unsigned command_reg = NITIO_Gi_Command_Reg(counter->counter_index);
2100         unsigned load_reg;
2101
2102         if(insn->n < 1) return 0;
2103         switch(channel)
2104         {
2105         case 0:
2106                 /* Unsafe if counter is armed.  Should probably check status and return -EBUSY if armed. */
2107                 /* Don't disturb load source select, just use whichever load register is already selected. */
2108                 load_reg = ni_tio_next_load_register(counter);
2109                 counter_dev->write_register(counter, data[0], load_reg);
2110                 counter_dev->write_register(counter, counter_dev->regs[command_reg] | Gi_Load_Bit, command_reg);
2111                 /* restore state of load reg to whatever the user set last set it to */
2112                 counter_dev->write_register(counter, counter_dev->regs[load_reg], load_reg);
2113                 break;
2114         case 1:
2115                 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = data[0];
2116                 counter_dev->write_register(counter, data[0], NITIO_Gi_LoadA_Reg(counter->counter_index));
2117                 break;
2118         case 2:
2119                 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = data[0];
2120                 counter_dev->write_register(counter, data[0], NITIO_Gi_LoadB_Reg(counter->counter_index));
2121                 break;
2122         default:
2123                 return -EINVAL;
2124                 break;
2125         }
2126         return 0;
2127 }
2128
2129 static void ni_tio_configure_dma(struct ni_gpct *counter, short enable, short read_not_write)
2130 {
2131         struct ni_gpct_device *counter_dev = counter->counter_dev;
2132
2133         switch(counter_dev->variant)
2134         {
2135         case ni_gpct_variant_e_series:
2136                 {
2137                         const unsigned input_select_reg = NITIO_Gi_Input_Select_Reg(counter->counter_index);
2138                         if(enable)
2139                         {
2140                                 if(read_not_write)
2141                                 {
2142                                         counter_dev->regs[input_select_reg] |= Gi_Read_Acknowledges_Irq;
2143                                         counter_dev->regs[input_select_reg] &= ~Gi_Write_Acknowledges_Irq;
2144                                 }else
2145                                 {
2146                                         counter_dev->regs[input_select_reg] &= ~Gi_Read_Acknowledges_Irq;
2147                                         counter_dev->regs[input_select_reg] |= Gi_Write_Acknowledges_Irq;
2148                                 }
2149                         }else
2150                         {
2151                                 counter_dev->regs[input_select_reg] &= ~(Gi_Read_Acknowledges_Irq | Gi_Write_Acknowledges_Irq);
2152                         }
2153                         counter_dev->write_register(counter, counter_dev->regs[input_select_reg], input_select_reg);
2154                 }
2155                 break;
2156         case ni_gpct_variant_m_series:
2157         case ni_gpct_variant_660x:
2158                 {
2159                         const unsigned gi_dma_config_reg = NITIO_Gi_DMA_Config_Reg(counter->counter_index);
2160
2161                         if(enable)
2162                         {
2163                                 counter_dev->regs[gi_dma_config_reg] |= Gi_DMA_Enable_Bit;
2164                                 counter_dev->regs[gi_dma_config_reg] |= Gi_DMA_Int_Bit;
2165                         }else
2166                         {
2167                                 counter_dev->regs[gi_dma_config_reg] &= ~Gi_DMA_Enable_Bit;
2168                                 counter_dev->regs[gi_dma_config_reg] &= ~Gi_DMA_Int_Bit;
2169                         }
2170                         if(read_not_write)
2171                         {
2172                                 counter_dev->regs[gi_dma_config_reg] &= ~Gi_DMA_Write_Bit;
2173                         }else
2174                         {
2175                                 counter_dev->regs[gi_dma_config_reg] |= Gi_DMA_Write_Bit;
2176                         }
2177                         counter_dev->write_register(counter, counter_dev->regs[gi_dma_config_reg], gi_dma_config_reg);
2178                 }
2179                 break;
2180         }
2181 }
2182
2183 static int ni_tio_input_cmd(struct ni_gpct *counter, comedi_async *async)
2184 {
2185         struct ni_gpct_device *counter_dev = counter->counter_dev;
2186         comedi_cmd *cmd = &async->cmd;
2187         const unsigned command_reg = NITIO_Gi_Command_Reg(counter->counter_index);
2188
2189         /* write alloc the entire buffer */
2190         comedi_buf_write_alloc(async, async->prealloc_bufsz);
2191         counter->mite_chan->dir = COMEDI_INPUT;
2192         switch(counter_dev->variant)
2193         {
2194         case ni_gpct_variant_m_series:
2195         case ni_gpct_variant_660x:
2196                 mite_prep_dma(counter->mite_chan, 32, 32);
2197                 break;
2198         case ni_gpct_variant_e_series:
2199                 mite_prep_dma(counter->mite_chan, 16, 32);
2200                 break;
2201         default:
2202                 BUG();
2203                 break;
2204         }
2205         counter_dev->regs[command_reg] &= ~Gi_Save_Trace_Bit;
2206         counter_dev->write_register(counter, counter_dev->regs[command_reg], command_reg);
2207         ni_tio_configure_dma(counter, 1, 1);
2208         mite_dma_arm(counter->mite_chan);
2209         return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
2210 }
2211
2212 static int ni_tio_output_cmd(struct ni_gpct *counter, comedi_async *async)
2213 {
2214         rt_printk("ni_tio: output commands not yet implemented.\n");
2215         return -ENOTSUPP;
2216
2217         counter->mite_chan->dir = COMEDI_OUTPUT;
2218         mite_prep_dma(counter->mite_chan, 32, 32);
2219         ni_tio_configure_dma(counter, 1, 0);
2220         mite_dma_arm(counter->mite_chan);
2221         return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
2222 }
2223
2224 int ni_tio_cmd(struct ni_gpct *counter, comedi_async *async)
2225 {
2226         comedi_cmd *cmd = &async->cmd;
2227         int retval;
2228
2229         if(counter->mite_chan == NULL)
2230         {
2231                 rt_printk("ni_tio: commands only supported with DMA.  Interrupt-driven commands not yet implemented.\n");
2232                 retval = -EIO;
2233         }else
2234         {
2235                 if(cmd->flags & CMDF_WRITE)
2236                 {
2237                         retval = ni_tio_output_cmd(counter, async);
2238                 }else
2239                 {
2240                         retval = ni_tio_input_cmd(counter, async);
2241                 }
2242         }
2243         return retval;
2244 }
2245
2246 int ni_tio_cmdtest(struct ni_gpct *counter)
2247 {
2248         return 0;
2249 }
2250
2251 int ni_tio_cancel(struct ni_gpct *counter)
2252 {
2253         ni_tio_arm(counter, 0, 0);
2254         if(counter->mite_chan)
2255         {
2256                 mite_dma_disarm(counter->mite_chan);
2257         }
2258         ni_tio_configure_dma(counter, 0, 0);
2259         return 0;
2260 }
2261
2262 EXPORT_SYMBOL_GPL(ni_tio_rinsn);
2263 EXPORT_SYMBOL_GPL(ni_tio_winsn);
2264 EXPORT_SYMBOL_GPL(ni_tio_cmd);
2265 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
2266 EXPORT_SYMBOL_GPL(ni_tio_cancel);
2267 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
2268 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
2269 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
2270 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);